I wrote this longish email with diagrams and what not and accidentally deleted it, so this one's shorter.. sorry :)
So I think this brings into question the value of doing more than a single buffer worth of prefetch in a loop which prefetches multiple parts of the buffer, right? I.e., it's suggesting that the best way to do this (if possible) is prefetch B-part1 compute on B-part0 prefetch B-part2 compute on B-part1 ... prefetch B-part(n) compute on B-part(n-1) compute on B-part(n) And the only time it works to do more than 1 vlib_buffer_t prefetch would be if the number of parts is 1 or something very close to 1. You mentioned seeing better performance, did you make any changes and measure positive results? It would be interesting to look at those changes to help illuminate the guidance. Looking for cache misses in a loop is probably useful in tuning this. I haven't done that yet, but it'll be interesting when I get to that point. :) Thanks, Chris. > On Apr 28, 2020, at 5:13 AM, Damjan Marion via lists.fd.io > <[email protected]> wrote: > > > Folks, > > At many places in the code we have cluster of prefetch instructions which > seems to be bad idea to do. > I already noticed that perfermance is better when prefetch instructions are > interleaved with other code, > And there is nice section explaining right that in the Intel Optimization > Manual. > > http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html > > Copy/paste from the document: > --- > It may seem convenient to cluster all of PREFETCH instructions at the > beginning of a loop body or before a loop, but this can lead to severe > performance degradation. In order to achieve the best possible performance, > PREFETCH instructions must be interspersed with other computational > instructions in the instruction sequence rather than clustered together. If > possible, they should also be placed apart from loads. This improves the > instruction level parallelism and reduces the potential instruction resource > stalls. In addition, this mixing reduces the pressure on the memory access > resources and in turn reduces the possibility of the prefetch retiring > without fetching data. > —-- > > — > Damjan
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