> Of course there's a PCI switch. My main purpose of leveraging SR-IOV with > VF allocation is to allow the internal eswitch on the Intel NIC to handle > switching in hardware
A PCIe switch is a different beast than the internal "Ethernet switch" you are mentioning. The PCIe topology in your server can be represented as a tree, with the root-complex port (usually the CPU) as the root and devices at the leaves. Internal vertices are PCIe switches. Simple servers usually do not have PCIe switches, ie devices are directly attached to the CPU root-complex port. In your case it looks like the PCIe topology is bit more complex. > So just to confirm, I need to expect 100% CPU utilization with VPP/DPDK + > IOMMU? Yes. In specific cases you can switch the interfaces in interrupt mode to avoid that, but then you are restricted to a single thread for now. > If so, what's the best way to monitor CPU-related performance > impact if I always see 100%? VPP has a command for this: ~# vppctl show run The metric to monitor is "Vectors/Call". Below 10, VPP is mostly idle. Between 10 and 80, VPP is using CPU for good. Above 100 you are CPU-constrained and will experience packet drops. > Also I want to confirm that > enable_unsafe_noiommu_mode still enables the performance benefits of SR- > IOV and the only tradeoff is the aforementioned isolation/security > concern? Yes, you benefit from SR-IOV and there should not be any perf impact. Best ben
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