That's the whole point of the assert: to prevent growing the data structure beyond 1 cacheline. If you do so, you'll access 2 cachelines instead of 1 in the common case, making it slower. Changing CLIB_CACHE_LINE_BYTES is a very bad idea as it will change the layout of many internal data structures, wasting memory and hurting prefetch.
Best ben > -----Original Message----- > From: vpp-dev@lists.fd.io <vpp-dev@lists.fd.io> On Behalf Of Vijay Kumar > Sent: lundi 20 décembre 2021 11:52 > To: vpp-dev <vpp-dev@lists.fd.io> > Subject: [vpp-dev] Adding new fields to ipsec_sa_t giving STATIC ASSERT > > Hi experts, > > I am facing a compilation issue due to the STATIC assert defined on > cacheline1 field in the ipsec_sa_t. > > I tried to add 2 new fields above the (ALIGN_MARK macro mentioned) for my > product specific use-case but I am unable to add because of this static > ASSERT > > /* data accessed by dataplane code should be above this comment */ > CLIB_CACHE_LINE_ALIGN_MARK (cacheline1); > > > It looks like I have to increase the CLIB_CACHE_LINE_BYTES which is (1 << > 6) 64 bytes? > > Will it have any impact on perf if it is made 128 (1 << 7)? > > > Regards. >
-=-=-=-=-=-=-=-=-=-=-=- Links: You receive all messages sent to this group. View/Reply Online (#20652): https://lists.fd.io/g/vpp-dev/message/20652 Mute This Topic: https://lists.fd.io/mt/87853862/21656 Group Owner: vpp-dev+ow...@lists.fd.io Unsubscribe: https://lists.fd.io/g/vpp-dev/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
