Title: [95684] trunk/Source/_javascript_Core
- Revision
- 95684
- Author
- barraclo...@apple.com
- Date
- 2011-09-21 16:49:24 -0700 (Wed, 21 Sep 2011)
Log Message
DFG JIT should be able to compile op_throw
https://bugs.webkit.org/show_bug.cgi?id=68571
Patch by Filip Pizlo <fpi...@apple.com> on 2011-09-21
Reviewed by Geoffrey Garen.
This compiles op_throw in the simplest way possible: it's an OSR
point back to the old JIT. This is a good step towards increasing
coverage, particularly on Kraken, but it's neutral because the
same functions that do throw also use some other unsupported
opcodes.
* dfg/DFGByteCodeParser.cpp:
(JSC::DFG::ByteCodeParser::parseBlock):
* dfg/DFGCapabilities.h:
(JSC::DFG::canCompileOpcode):
* dfg/DFGNode.h:
* dfg/DFGPropagator.cpp:
(JSC::DFG::Propagator::propagateNodePredictions):
* dfg/DFGSpeculativeJIT.cpp:
(JSC::DFG::SpeculativeJIT::compile):
Modified Paths
Diff
Modified: trunk/Source/_javascript_Core/ChangeLog (95683 => 95684)
--- trunk/Source/_javascript_Core/ChangeLog 2011-09-21 23:46:09 UTC (rev 95683)
+++ trunk/Source/_javascript_Core/ChangeLog 2011-09-21 23:49:24 UTC (rev 95684)
@@ -122,6 +122,18 @@
2011-09-21 Gavin Barraclough <barraclo...@apple.com>
+ Add X86 GPRInfo for DFG JIT.
+ https://bugs.webkit.org/show_bug.cgi?id=68586
+
+ Reviewed by Geoff Garen.
+
+ * dfg/DFGGPRInfo.h:
+ (JSC::DFG::GPRInfo::toRegister):
+ (JSC::DFG::GPRInfo::toIndex):
+ (JSC::DFG::GPRInfo::debugName):
+
+2011-09-21 Gavin Barraclough <barraclo...@apple.com>
+
Should support value profiling on CPU(X86)
https://bugs.webkit.org/show_bug.cgi?id=68575
Modified: trunk/Source/_javascript_Core/dfg/DFGGPRInfo.h (95683 => 95684)
--- trunk/Source/_javascript_Core/dfg/DFGGPRInfo.h 2011-09-21 23:46:09 UTC (rev 95683)
+++ trunk/Source/_javascript_Core/dfg/DFGGPRInfo.h 2011-09-21 23:49:24 UTC (rev 95684)
@@ -36,12 +36,72 @@
typedef MacroAssembler::RegisterID GPRReg;
#define InvalidGPRReg ((GPRReg)-1)
+#if CPU(X86)
+
class GPRInfo {
public:
typedef GPRReg RegisterType;
+ static const unsigned numberOfRegisters = 4;
+
+ // These registers match the baseline JIT.
+ static const GPRReg cachedResultRegister = X86Registers::eax;
+ static const GPRReg timeoutCheckRegister = X86Registers::esi;
+ static const GPRReg callFrameRegister = X86Registers::edi;
+ // Temporary registers.
+ static const GPRReg regT0 = X86Registers::eax;
+ static const GPRReg regT1 = X86Registers::edx;
+ static const GPRReg regT2 = X86Registers::ecx;
+ static const GPRReg regT3 = X86Registers::ebx;
+ // These constants provide the names for the general purpose argument & return value registers.
+ static const GPRReg argumentGPR0 = X86Registers::ecx; // regT2
+ static const GPRReg argumentGPR1 = X86Registers::edx; // regT1
+ static const GPRReg returnValueGPR = X86Registers::eax; // regT0
+ static const GPRReg returnValueGPR2 = X86Registers::edx; // regT1
+
+ static GPRReg toRegister(unsigned index)
+ {
+ ASSERT(index < numberOfRegisters);
+ static const GPRReg registerForIndex[numberOfRegisters] = { regT0, regT1, regT2, regT3, };
+ return registerForIndex[index];
+ }
+
+ static unsigned toIndex(GPRReg reg)
+ {
+ ASSERT(reg != InvalidGPRReg);
+ ASSERT(reg < 8);
+ static const unsigned indexForRegister[8] = { 0, 2, 1, 3, InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex };
+ unsigned result = indexForRegister[reg];
+ ASSERT(result != InvalidIndex);
+ return result;
+ }
+
+#ifndef NDEBUG
+ static const char* debugName(GPRReg reg)
+ {
+ ASSERT(reg != InvalidGPRReg);
+ ASSERT(reg < 8);
+ static const char* nameForRegister[8] = {
+ "rax", "rcx", "rdx", "rbx",
+ "rsp", "rbp", "rsi", "rdi",
+ };
+ return nameForRegister[reg];
+ }
+#endif
+private:
+
+ static const unsigned InvalidIndex = 0xffffffff;
+};
+
+#endif
+
+#if CPU(X86_64)
+
+class GPRInfo {
+public:
+ typedef GPRReg RegisterType;
static const unsigned numberOfRegisters = 9;
- // These registers match the old JIT.
+ // These registers match the baseline JIT.
static const GPRReg cachedResultRegister = X86Registers::eax;
static const GPRReg timeoutCheckRegister = X86Registers::r12;
static const GPRReg callFrameRegister = X86Registers::r13;
@@ -101,6 +161,8 @@
static const unsigned InvalidIndex = 0xffffffff;
};
+#endif
+
typedef RegisterBank<GPRInfo>::iterator gpr_iterator;
} } // namespace JSC::DFG
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