[webkit-changes] [203226] trunk/Source/JavaScriptCore

[commit-queue]

Title: [203226] trunk/Source/_javascript_Core

Revision

203226

Author

commit-qu...@webkit.org

Date

2016-07-14 10:38:16 -0700 (Thu, 14 Jul 2016)

Log Message

[mips] Handle properly unaligned halfword load
https://bugs.webkit.org/show_bug.cgi?id=153226

Patch by Julien Brianceau <jbria...@cisco.com> on 2016-07-14
Reviewed by Michael Catanzaro.

Waiting for the kernel to silently fix-up unaligned accesses is
not efficient, so let's provide an implementation of load16Unaligned
in mips macro assembler.

Performance improvement seen with SunSpider's regexp-dna test.

* assembler/MacroAssemblerMIPS.h:
(JSC::MacroAssemblerMIPS::load16Unaligned):
(JSC::MacroAssemblerMIPS::load32WithUnalignedHalfWords):

Modified Paths

• trunk/Source/_javascript_Core/ChangeLog
• trunk/Source/_javascript_Core/assembler/MacroAssemblerMIPS.h

Diff

Modified: trunk/Source/_javascript_Core/ChangeLog (203225 => 203226)

--- trunk/Source/_javascript_Core/ChangeLog	2016-07-14 17:26:00 UTC (rev 203225)
+++ trunk/Source/_javascript_Core/ChangeLog	2016-07-14 17:38:16 UTC (rev 203226)
@@ -1,3 +1,20 @@
+2016-07-14  Julien Brianceau  <jbria...@cisco.com>
+
+        [mips] Handle properly unaligned halfword load
+        https://bugs.webkit.org/show_bug.cgi?id=153226
+
+        Reviewed by Michael Catanzaro.
+
+        Waiting for the kernel to silently fix-up unaligned accesses is
+        not efficient, so let's provide an implementation of load16Unaligned
+        in mips macro assembler.
+
+        Performance improvement seen with SunSpider's regexp-dna test.
+
+        * assembler/MacroAssemblerMIPS.h:
+        (JSC::MacroAssemblerMIPS::load16Unaligned):
+        (JSC::MacroAssemblerMIPS::load32WithUnalignedHalfWords):
+
 2016-07-14  Youenn Fablet  <you...@apple.com>
 
         DOM value iterable interfaces should use Array prototype methods

Modified: trunk/Source/_javascript_Core/assembler/MacroAssemblerMIPS.h (203225 => 203226)

--- trunk/Source/_javascript_Core/assembler/MacroAssemblerMIPS.h	2016-07-14 17:26:00 UTC (rev 203225)
+++ trunk/Source/_javascript_Core/assembler/MacroAssemblerMIPS.h	2016-07-14 17:38:16 UTC (rev 203226)
@@ -822,7 +822,53 @@
 
     void load16Unaligned(BaseIndex address, RegisterID dest)
     {
-        load16(address, dest);
+        if (address.offset >= -32768 && address.offset <= 32767 && !m_fixedWidth) {
+            /*
+                sll     addrtemp, address.index, address.scale
+                addu    addrtemp, addrtemp, address.base
+                lbu     immTemp, address.offset+x(addrtemp) (x=0 for LE, x=1 for BE)
+                lbu     dest, address.offset+x(addrtemp)    (x=1 for LE, x=0 for BE)
+                sll     dest, dest, 8
+                or      dest, dest, immTemp
+            */
+            m_assembler.sll(addrTempRegister, address.index, address.scale);
+            m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
+#if CPU(BIG_ENDIAN)
+            m_assembler.lbu(immTempRegister, addrTempRegister, address.offset + 1);
+            m_assembler.lbu(dest, addrTempRegister, address.offset);
+#else
+            m_assembler.lbu(immTempRegister, addrTempRegister, address.offset);
+            m_assembler.lbu(dest, addrTempRegister, address.offset + 1);
+#endif
+            m_assembler.sll(dest, dest, 8);
+            m_assembler.orInsn(dest, dest, immTempRegister);
+        } else {
+            /*
+                sll     addrTemp, address.index, address.scale
+                addu    addrTemp, addrTemp, address.base
+                lui     immTemp, address.offset >> 16
+                ori     immTemp, immTemp, address.offset & 0xffff
+                addu    addrTemp, addrTemp, immTemp
+                lbu     immTemp, x(addrtemp) (x=0 for LE, x=1 for BE)
+                lbu     dest, x(addrtemp)    (x=1 for LE, x=0 for BE)
+                sll     dest, dest, 8
+                or      dest, dest, immTemp
+            */
+            m_assembler.sll(addrTempRegister, address.index, address.scale);
+            m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
+            m_assembler.lui(immTempRegister, address.offset >> 16);
+            m_assembler.ori(immTempRegister, immTempRegister, address.offset);
+            m_assembler.addu(addrTempRegister, addrTempRegister, immTempRegister);
+#if CPU(BIG_ENDIAN)
+            m_assembler.lbu(immTempRegister, addrTempRegister, 1);
+            m_assembler.lbu(dest, addrTempRegister, 0);
+#else
+            m_assembler.lbu(immTempRegister, addrTempRegister, 0);
+            m_assembler.lbu(dest, addrTempRegister, 1);
+#endif
+            m_assembler.sll(dest, dest, 8);
+            m_assembler.orInsn(dest, dest, immTempRegister);
+        }
     }
 
     void load32WithUnalignedHalfWords(BaseIndex address, RegisterID dest)

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