Diff
Modified: trunk/Source/_javascript_Core/ChangeLog (222650 => 222651)
--- trunk/Source/_javascript_Core/ChangeLog 2017-09-29 12:33:46 UTC (rev 222650)
+++ trunk/Source/_javascript_Core/ChangeLog 2017-09-29 16:47:42 UTC (rev 222651)
@@ -1,3 +1,16 @@
+2017-09-29 Commit Queue <[email protected]>
+
+ Unreviewed, rolling out r222625.
+ https://bugs.webkit.org/show_bug.cgi?id=177664
+
+ causes crashes on iOS (Requested by pizlo-mbp on #webkit).
+
+ Reverted changeset:
+
+ "Enable gigacage on iOS"
+ https://bugs.webkit.org/show_bug.cgi?id=177586
+ http://trac.webkit.org/changeset/222625
+
2017-09-28 Mark Lam <[email protected]>
test262: Unexpected passes after r222617 and r222618.
Modified: trunk/Source/_javascript_Core/offlineasm/arm64.rb (222650 => 222651)
--- trunk/Source/_javascript_Core/offlineasm/arm64.rb 2017-09-29 12:33:46 UTC (rev 222650)
+++ trunk/Source/_javascript_Core/offlineasm/arm64.rb 2017-09-29 16:47:42 UTC (rev 222651)
@@ -260,31 +260,6 @@
newList
end
-def arm64LowerLabelReferences(list)
- newList = []
- list.each {
- | node |
- if node.is_a? Instruction
- case node.opcode
- when "loadi", "loadis", "loadp", "loadq", "loadb", "loadbs", "loadh", "loadhs"
- labelRef = node.operands[0]
- if labelRef.is_a? LabelReference
- tmp = Tmp.new(node.codeOrigin, :gpr)
- newList << Instruction.new(codeOrigin, "globaladdr", [LabelReference.new(node.codeOrigin, labelRef.label), tmp])
- newList << Instruction.new(codeOrigin, node.opcode, [Address.new(node.codeOrigin, tmp, Immediate.new(node.codeOrigin, labelRef.offset)), node.operands[1]])
- else
- newList << node
- end
- else
- newList << node
- end
- else
- newList << node
- end
- }
- newList
-end
-
# Workaround for Cortex-A53 erratum (835769)
def arm64CortexA53Fix835769(list)
newList = []
@@ -321,7 +296,6 @@
result = riscLowerHardBranchOps64(result)
result = riscLowerShiftOps(result)
result = arm64LowerMalformedLoadStoreAddresses(result)
- result = arm64LowerLabelReferences(result)
result = riscLowerMalformedAddresses(result) {
| node, address |
case node.opcode
@@ -930,15 +904,6 @@
$asm.putStr("#if CPU(ARM64_CORTEXA53)")
$asm.puts "nop"
$asm.putStr("#endif")
- when "globaladdr"
- uid = $asm.newUID
- $asm.puts "L_offlineasm_loh_adrp_#{uid}:"
- $asm.puts "adrp #{operands[1].arm64Operand(:ptr)}, #{operands[0].asmLabel}@GOTPAGE"
- $asm.puts "L_offlineasm_loh_ldr_#{uid}:"
- $asm.puts "ldr #{operands[1].arm64Operand(:ptr)}, [#{operands[1].arm64Operand(:ptr)}, #{operands[0].asmLabel}@GOTPAGEOFF]"
- $asm.deferAction {
- $asm.puts ".loh AdrpLdrGot L_offlineasm_loh_adrp_#{uid}, L_offlineasm_loh_ldr_#{uid}"
- }
else
lowerDefault
end
Modified: trunk/Source/_javascript_Core/offlineasm/asm.rb (222650 => 222651)
--- trunk/Source/_javascript_Core/offlineasm/asm.rb 2017-09-29 12:33:46 UTC (rev 222650)
+++ trunk/Source/_javascript_Core/offlineasm/asm.rb 2017-09-29 16:47:42 UTC (rev 222651)
@@ -46,8 +46,6 @@
@codeOrigin = nil
@numLocalLabels = 0
@numGlobalLabels = 0
- @deferredActions = []
- @count = 0
@newlineSpacerState = :none
@lastlabel = ""
@@ -75,23 +73,10 @@
putsProcEndIfNeeded
end
putsLastComment
- @deferredActions.each {
- | action |
- action.call()
- }
@outp.puts "OFFLINE_ASM_END" if !$emitWinAsm
@state = :cpp
end
- def deferAction(&proc)
- @deferredActions << proc
- end
-
- def newUID
- @count += 1
- @count
- end
-
def inAsm
enterAsm
yield
Modified: trunk/Source/_javascript_Core/offlineasm/instructions.rb (222650 => 222651)
--- trunk/Source/_javascript_Core/offlineasm/instructions.rb 2017-09-29 12:33:46 UTC (rev 222650)
+++ trunk/Source/_javascript_Core/offlineasm/instructions.rb 2017-09-29 16:47:42 UTC (rev 222651)
@@ -267,8 +267,7 @@
ARM64_INSTRUCTIONS =
[
"pcrtoaddr", # Address from PC relative offset - adr instruction
- "nopFixCortexA53Err835769", # nop on Cortex-A53 (nothing otherwise)
- "globaladdr"
+ "nopFixCortexA53Err835769" # nop on Cortex-A53 (nothing otherwise)
]
RISC_INSTRUCTIONS =
Modified: trunk/Source/bmalloc/ChangeLog (222650 => 222651)
--- trunk/Source/bmalloc/ChangeLog 2017-09-29 12:33:46 UTC (rev 222650)
+++ trunk/Source/bmalloc/ChangeLog 2017-09-29 16:47:42 UTC (rev 222651)
@@ -1,3 +1,16 @@
+2017-09-29 Commit Queue <[email protected]>
+
+ Unreviewed, rolling out r222625.
+ https://bugs.webkit.org/show_bug.cgi?id=177664
+
+ causes crashes on iOS (Requested by pizlo-mbp on #webkit).
+
+ Reverted changeset:
+
+ "Enable gigacage on iOS"
+ https://bugs.webkit.org/show_bug.cgi?id=177586
+ http://trac.webkit.org/changeset/222625
+
2017-09-28 Filip Pizlo <[email protected]>
Enable gigacage on iOS
Modified: trunk/Source/bmalloc/bmalloc/Gigacage.h (222650 => 222651)
--- trunk/Source/bmalloc/bmalloc/Gigacage.h 2017-09-29 12:33:46 UTC (rev 222650)
+++ trunk/Source/bmalloc/bmalloc/Gigacage.h 2017-09-29 16:47:42 UTC (rev 222651)
@@ -32,17 +32,9 @@
#include <cstddef>
#include <inttypes.h>
-#if BCPU(ARM64)
-// FIXME: This can probably be a lot bigger on iOS. I just haven't tried to make it bigger yet.
-// https://bugs.webkit.org/show_bug.cgi?id=177605
-#define PRIMITIVE_GIGACAGE_SIZE 0x40000000llu
-#define JSVALUE_GIGACAGE_SIZE 0x40000000llu
-#define STRING_GIGACAGE_SIZE 0x40000000llu
-#else
#define PRIMITIVE_GIGACAGE_SIZE 0x800000000llu
#define JSVALUE_GIGACAGE_SIZE 0x400000000llu
#define STRING_GIGACAGE_SIZE 0x400000000llu
-#endif
#define GIGACAGE_SIZE_TO_MASK(size) ((size) - 1)
@@ -50,15 +42,9 @@
#define JSVALUE_GIGACAGE_MASK GIGACAGE_SIZE_TO_MASK(JSVALUE_GIGACAGE_SIZE)
#define STRING_GIGACAGE_MASK GIGACAGE_SIZE_TO_MASK(STRING_GIGACAGE_SIZE)
-#if BCPU(ARM64)
-// FIXME: There is no good reason for ARM64 to be special.
-// https://bugs.webkit.org/show_bug.cgi?id=177605
-#define PRIMITIVE_GIGACAGE_RUNWAY 0
-#else
// FIXME: Consider making this 32GB, in case unsigned 32-bit indices find their way into indexed accesses.
// https://bugs.webkit.org/show_bug.cgi?id=175062
#define PRIMITIVE_GIGACAGE_RUNWAY (16llu * 1024 * 1024 * 1024)
-#endif
// FIXME: Reconsider this.
// https://bugs.webkit.org/show_bug.cgi?id=175921
@@ -65,17 +51,13 @@
#define JSVALUE_GIGACAGE_RUNWAY 0
#define STRING_GIGACAGE_RUNWAY 0
-#if BOS(DARWIN) && (BCPU(ARM64) || BCPU(X86_64))
+#if BOS(DARWIN) && BCPU(X86_64)
#define GIGACAGE_ENABLED 1
#else
#define GIGACAGE_ENABLED 0
#endif
-#if BCPU(ARM64)
-#define GIGACAGE_BASE_PTRS_SIZE 16384
-#else
-#define GIGACAGE_BASE_PTRS_SIZE 4096
-#endif
+#define GIGACAGE_BASE_PTRS_SIZE 8192
extern "C" BEXPORT char g_gigacageBasePtrs[GIGACAGE_BASE_PTRS_SIZE] __attribute__((aligned(GIGACAGE_BASE_PTRS_SIZE)));
