Title: [240241] trunk/Source/_javascript_Core
Revision
240241
Author
[email protected]
Date
2019-01-21 12:50:59 -0800 (Mon, 21 Jan 2019)

Log Message

[JSC] sub op with 0 should be optimized
https://bugs.webkit.org/show_bug.cgi?id=190751

Reviewed by Mark Lam.

LLInt sometimes emit `subp 0, %rxx`. For example, `maxFrameExtentForSlowPathCall` is 0 in X86_64, ARM64, and ARM64E.
So `subp maxFrameExtentForSlowPathCall sp` becomes `subp 0, %rsp`. While `addp 0, %rsp` is removed in offlineasm,
sub operation does not have such an optimization. This patch applies the same optimization to sub operation already
done in add operation. Since the CPU flags changed in offlineasm's these operations are not considered (if these flags
are required, we use special branch operations instead), this optimization is sane.

One problem is that zero-extension of the 32bit register in 64bit architecture. If the instruction emission is skipped,
this won't be happen. Currently, we align our sub to add operation: we skip emission in this case.

* offlineasm/arm64.rb:
* offlineasm/x86.rb:

Modified Paths

Diff

Modified: trunk/Source/_javascript_Core/ChangeLog (240240 => 240241)


--- trunk/Source/_javascript_Core/ChangeLog	2019-01-21 20:15:53 UTC (rev 240240)
+++ trunk/Source/_javascript_Core/ChangeLog	2019-01-21 20:50:59 UTC (rev 240241)
@@ -1,3 +1,22 @@
+2019-01-20  Yusuke Suzuki  <[email protected]>
+
+        [JSC] sub op with 0 should be optimized
+        https://bugs.webkit.org/show_bug.cgi?id=190751
+
+        Reviewed by Mark Lam.
+
+        LLInt sometimes emit `subp 0, %rxx`. For example, `maxFrameExtentForSlowPathCall` is 0 in X86_64, ARM64, and ARM64E.
+        So `subp maxFrameExtentForSlowPathCall sp` becomes `subp 0, %rsp`. While `addp 0, %rsp` is removed in offlineasm,
+        sub operation does not have such an optimization. This patch applies the same optimization to sub operation already
+        done in add operation. Since the CPU flags changed in offlineasm's these operations are not considered (if these flags
+        are required, we use special branch operations instead), this optimization is sane.
+
+        One problem is that zero-extension of the 32bit register in 64bit architecture. If the instruction emission is skipped,
+        this won't be happen. Currently, we align our sub to add operation: we skip emission in this case.
+
+        * offlineasm/arm64.rb:
+        * offlineasm/x86.rb:
+
 2019-01-20  Saam Barati  <[email protected]>
 
         DFG: When inlining DataView set* intrinsics we need to set undefined as our result

Modified: trunk/Source/_javascript_Core/offlineasm/arm64.rb (240240 => 240241)


--- trunk/Source/_javascript_Core/offlineasm/arm64.rb	2019-01-21 20:15:53 UTC (rev 240240)
+++ trunk/Source/_javascript_Core/offlineasm/arm64.rb	2019-01-21 20:50:59 UTC (rev 240241)
@@ -460,8 +460,8 @@
         raise unless operands[2].register?
         
         if operands[0].immediate?
-            if operands[0].value == 0 and flag !~ /s$/
-                unless operands[1] == operands[2]
+            if operands[0].value == 0 and opcode !~ /s$/
+                if operands[1] != operands[2]
                     $asm.puts "mov #{arm64FlippedOperands(operands[1..2], kind)}"
                 end
             else
@@ -496,6 +496,30 @@
     $asm.puts "madd #{arm64TACOperands(operands, kind)}, #{arm64GPRName('xzr', kind)}"
 end
 
+def emitARM64Sub(opcode, operands, kind)
+    if operands.size == 3
+        raise unless operands[0].register?
+        raise unless operands[2].register?
+
+        if operands[1].immediate?
+            if operands[1].value == 0 and opcode !~ /s$/
+                if operands[0] != operands[2]
+                    $asm.puts "mov #{arm64FlippedOperands([operands[0], operands[2]], kind)}"
+                end
+                return
+            end
+        end
+    end
+
+    if operands.size == 2
+        if operands[0].immediate? and operands[0].value == 0 and opcode !~ /s$/
+            return
+        end
+    end
+
+    emitARM64TAC(opcode, operands, kind)
+end
+
 def emitARM64Unflipped(opcode, operands, kind)
     $asm.puts "#{opcode} #{arm64Operands(operands, kind)}"
 end
@@ -655,13 +679,13 @@
         when "mulq"
             emitARM64Mul('mul', operands, :quad)
         when "subi"
-            emitARM64TAC("sub", operands, :word)
+            emitARM64Sub("sub", operands, :word)
         when "subp"
-            emitARM64TAC("sub", operands, :ptr)
+            emitARM64Sub("sub", operands, :ptr)
         when "subq"
-            emitARM64TAC("sub", operands, :quad)
+            emitARM64Sub("sub", operands, :quad)
         when "subis"
-            emitARM64TAC("subs", operands, :word)
+            emitARM64Sub("subs", operands, :word)
         when "negi"
             $asm.puts "sub #{operands[0].arm64Operand(:word)}, wzr, #{operands[0].arm64Operand(:word)}"
         when "negp"

Modified: trunk/Source/_javascript_Core/offlineasm/x86.rb (240240 => 240241)


--- trunk/Source/_javascript_Core/offlineasm/x86.rb	2019-01-21 20:15:53 UTC (rev 240240)
+++ trunk/Source/_javascript_Core/offlineasm/x86.rb	2019-01-21 20:50:59 UTC (rev 240241)
@@ -761,7 +761,7 @@
             raise unless operands[1].is_a? RegisterID
             raise unless operands[2].is_a? RegisterID
             if operands[0].value == 0
-                unless operands[1] == operands[2]
+                if operands[1] != operands[2]
                     $asm.puts "mov#{x86Suffix(kind)} #{orderOperands(operands[1].x86Operand(kind), operands[2].x86Operand(kind))}"
                 end
             else
@@ -787,12 +787,31 @@
     end
     
     def handleX86Sub(kind)
-        if operands.size == 3 and operands[1] == operands[2]
-            $asm.puts "neg#{x86Suffix(kind)} #{operands[2].x86Operand(kind)}"
-            $asm.puts "add#{x86Suffix(kind)} #{orderOperands(operands[0].x86Operand(kind), operands[2].x86Operand(kind))}"
-        else
-            handleX86Op("sub#{x86Suffix(kind)}", kind)
+        if operands.size == 3
+            if Immediate.new(nil, 0) == operands[1]
+                raise unless operands[0].is_a? RegisterID
+                raise unless operands[2].is_a? RegisterID
+                if operands[0] != operands[2]
+                    $asm.puts "mov#{x86Suffix(kind)} #{orderOperands(operands[0].x86Operand(kind), operands[2].x86Operand(kind))}"
+                end
+                return
+            end
+            if operands[1] == operands[2]
+                $asm.puts "neg#{x86Suffix(kind)} #{operands[2].x86Operand(kind)}"
+                if Immediate.new(nil, 0) != operands[0]
+                    $asm.puts "add#{x86Suffix(kind)} #{orderOperands(operands[0].x86Operand(kind), operands[2].x86Operand(kind))}"
+                end
+                return
+            end
         end
+
+        if operands.size == 2
+            if Immediate.new(nil, 0) == operands[0]
+                return
+            end
+        end
+
+        handleX86Op("sub#{x86Suffix(kind)}", kind)
     end
     
     def handleX86Mul(kind)
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