Log Message
[ARM64E]: Add disassembler support for authenticated instructions https://bugs.webkit.org/show_bug.cgi?id=198562
Reviewed by Keith Miller. Added support for all the instructions supported in ARM64EAssembler.h. * disassembler/ARM64/A64DOpcode.cpp: (JSC::ARM64Disassembler::A64DOpcodeDataProcessing1Source::format): (JSC::ARM64Disassembler::A64DOpcodeDataProcessing2Source::format): (JSC::ARM64Disassembler::A64DOpcodeHint::format): (JSC::ARM64Disassembler::A64DOpcodeHint::opName): (JSC::ARM64Disassembler::A64DOpcodeLoadStoreAuthenticated::format): (JSC::ARM64Disassembler::A64DOpcodeUnconditionalBranchRegister::authOpName): (JSC::ARM64Disassembler::A64DOpcodeUnconditionalBranchRegister::format): * disassembler/ARM64/A64DOpcode.h: (JSC::ARM64Disassembler::A64DOpcodeDataProcessing2Source::opNameIndex): (JSC::ARM64Disassembler::A64DOpcodeLoadStoreAuthenticated::opName): (JSC::ARM64Disassembler::A64DOpcodeLoadStoreAuthenticated::opNum): (JSC::ARM64Disassembler::A64DOpcodeLoadStoreAuthenticated::mBit): (JSC::ARM64Disassembler::A64DOpcodeLoadStoreAuthenticated::sBit): (JSC::ARM64Disassembler::A64DOpcodeLoadStoreAuthenticated::wBit): (JSC::ARM64Disassembler::A64DOpcodeLoadStoreAuthenticated::immediate10): (JSC::ARM64Disassembler::A64DOpcodeUnconditionalBranchRegister::authOpCode): (JSC::ARM64Disassembler::A64DOpcodeUnconditionalBranchRegister::op2): (JSC::ARM64Disassembler::A64DOpcodeUnconditionalBranchRegister::op3): (JSC::ARM64Disassembler::A64DOpcodeUnconditionalBranchRegister::op4): (JSC::ARM64Disassembler::A64DOpcodeUnconditionalBranchRegister::mBit): (JSC::ARM64Disassembler::A64DOpcodeUnconditionalBranchRegister::rm): (JSC::ARM64Disassembler::A64DOpcodeHint::opName): Deleted.
Modified Paths
Diff
Modified: trunk/Source/_javascript_Core/ChangeLog (246146 => 246147)
--- trunk/Source/_javascript_Core/ChangeLog 2019-06-06 08:58:04 UTC (rev 246146)
+++ trunk/Source/_javascript_Core/ChangeLog 2019-06-06 09:31:40 UTC (rev 246147)
@@ -1,3 +1,36 @@
+2019-06-06 Michael Saboff <[email protected]>
+
+ [ARM64E]: Add disassembler support for authenticated instructions
+ https://bugs.webkit.org/show_bug.cgi?id=198562
+
+ Reviewed by Keith Miller.
+
+ Added support for all the instructions supported in ARM64EAssembler.h.
+
+ * disassembler/ARM64/A64DOpcode.cpp:
+ (JSC::ARM64Disassembler::A64DOpcodeDataProcessing1Source::format):
+ (JSC::ARM64Disassembler::A64DOpcodeDataProcessing2Source::format):
+ (JSC::ARM64Disassembler::A64DOpcodeHint::format):
+ (JSC::ARM64Disassembler::A64DOpcodeHint::opName):
+ (JSC::ARM64Disassembler::A64DOpcodeLoadStoreAuthenticated::format):
+ (JSC::ARM64Disassembler::A64DOpcodeUnconditionalBranchRegister::authOpName):
+ (JSC::ARM64Disassembler::A64DOpcodeUnconditionalBranchRegister::format):
+ * disassembler/ARM64/A64DOpcode.h:
+ (JSC::ARM64Disassembler::A64DOpcodeDataProcessing2Source::opNameIndex):
+ (JSC::ARM64Disassembler::A64DOpcodeLoadStoreAuthenticated::opName):
+ (JSC::ARM64Disassembler::A64DOpcodeLoadStoreAuthenticated::opNum):
+ (JSC::ARM64Disassembler::A64DOpcodeLoadStoreAuthenticated::mBit):
+ (JSC::ARM64Disassembler::A64DOpcodeLoadStoreAuthenticated::sBit):
+ (JSC::ARM64Disassembler::A64DOpcodeLoadStoreAuthenticated::wBit):
+ (JSC::ARM64Disassembler::A64DOpcodeLoadStoreAuthenticated::immediate10):
+ (JSC::ARM64Disassembler::A64DOpcodeUnconditionalBranchRegister::authOpCode):
+ (JSC::ARM64Disassembler::A64DOpcodeUnconditionalBranchRegister::op2):
+ (JSC::ARM64Disassembler::A64DOpcodeUnconditionalBranchRegister::op3):
+ (JSC::ARM64Disassembler::A64DOpcodeUnconditionalBranchRegister::op4):
+ (JSC::ARM64Disassembler::A64DOpcodeUnconditionalBranchRegister::mBit):
+ (JSC::ARM64Disassembler::A64DOpcodeUnconditionalBranchRegister::rm):
+ (JSC::ARM64Disassembler::A64DOpcodeHint::opName): Deleted.
+
2019-06-05 Justin Michaud <[email protected]>
[WASM-References] Add support for Anyref tables, Table.get and Table.set (for Anyref only).
Modified: trunk/Source/_javascript_Core/disassembler/ARM64/A64DOpcode.cpp (246146 => 246147)
--- trunk/Source/_javascript_Core/disassembler/ARM64/A64DOpcode.cpp 2019-06-06 08:58:04 UTC (rev 246146)
+++ trunk/Source/_javascript_Core/disassembler/ARM64/A64DOpcode.cpp 2019-06-06 09:31:40 UTC (rev 246147)
@@ -95,6 +95,7 @@
OPCODE_GROUP_ENTRY(0x17, A64DOpcodeTestAndBranchImmediate),
OPCODE_GROUP_ENTRY(0x18, A64DOpcodeLoadStoreImmediate),
OPCODE_GROUP_ENTRY(0x18, A64DOpcodeLoadStoreRegisterOffset),
+ OPCODE_GROUP_ENTRY(0x18, A64DOpcodeLoadStoreAuthenticated),
OPCODE_GROUP_ENTRY(0x19, A64DOpcodeLoadStoreUnsignedImmediate),
OPCODE_GROUP_ENTRY(0x1a, A64DOpcodeConditionalSelect),
OPCODE_GROUP_ENTRY(0x1a, A64DOpcodeDataProcessing1Source),
@@ -455,6 +456,12 @@
const char* const A64DOpcodeDataProcessing1Source::s_opNames[8] = {
"rbit", "rev16", "rev32", "rev", "clz", "cls", 0, 0
};
+
+const char* const A64DOpcodeDataProcessing1Source::s_pacAutOpNames[18] = {
+ "pacia", "pacib", "pacda", "pacdb", "autia", "autib", "autda", "autdb",
+ "paciza", "pacizb", "pacdza", "pacdzb", "autiza", "autizb", "autdza", "autdzb",
+ "xpaci", "xpacd"
+};
const char* A64DOpcodeDataProcessing1Source::format()
{
@@ -461,6 +468,19 @@
if (sBit())
return A64DOpcode::format();
+ if (opCode2() == 1 && is64Bit() && opCode() <= 0x1001) {
+ if (opCode() <= 0x00111 || rt() == 0x11111) {
+ appendInstructionName(s_pacAutOpNames[opCode()]);
+ appendZROrRegisterName(rd(), is64Bit());
+ if (opCode() <= 0x00111) {
+ appendSeparator();
+ appendZROrRegisterName(rn(), is64Bit());
+ }
+ return m_formatBuffer;
+ }
+ return A64DOpcode::format();
+ }
+
if (opCode2())
return A64DOpcode::format();
@@ -484,8 +504,10 @@
return m_formatBuffer;
}
-const char* const A64DOpcodeDataProcessing2Source::s_opNames[8] = {
- 0, 0, "udiv", "sdiv", "lsl", "lsr", "asr", "ror" // We use the pseudo-op names for the shift/rotate instructions
+const char* const A64DOpcodeDataProcessing2Source::s_opNames[16] = {
+ // We use the pseudo-op names for the shift/rotate instructions
+ 0, 0, "udiv", "sdiv", 0, 0, 0, 0,
+ "lsl", "lsr", "asr", "ror", 0, "pacga", 0, 0
};
const char* A64DOpcodeDataProcessing2Source::format()
@@ -499,10 +521,14 @@
if (opCode() & 0x30)
return A64DOpcode::format();
- if ((opCode() & 0x34) == 0x4)
+ if ((opCode() & 0x3c) == 0x4)
return A64DOpcode::format();
- appendInstructionName(opName());
+ const char* opcodeName = opName();
+ if (!opcodeName)
+ return A64DOpcode::format();
+
+ appendInstructionName(opcodeName);
appendZROrRegisterName(rd(), is64Bit());
appendSeparator();
appendZROrRegisterName(rn(), is64Bit());
@@ -958,8 +984,11 @@
return m_formatBuffer;
}
-const char* const A64DOpcodeHint::s_opNames[6] = {
- "nop", "yield", "wfe", "wfi", "sev", "sevl"
+const char* const A64DOpcodeHint::s_opNames[32] = {
+ "nop", "yield", "wfe", "wfi", "sev", "sevl", 0, "xpaclri",
+ "pacia1716", 0, "pacib1716", 0, "autia1716", 0, "autib1716", 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ "paciaz", "paciasp", "pacibz", "pacibsp", "autiaz", "autiasp", "autibz", "autibsp"
};
const char* A64DOpcodeHint::format()
@@ -966,12 +995,21 @@
{
appendInstructionName(opName());
- if (immediate7() > 5)
+ if (immediate7() >= 32 || !s_opNames[immediate7()])
appendUnsignedImmediate(immediate7());
return m_formatBuffer;
}
+const char* A64DOpcodeHint::opName()
+{
+ const char* opName = (immediate7() < 32 ? s_opNames[immediate7()] : 0);
+ if (!opName)
+ return "hint";
+
+ return opName;
+}
+
const char* const A64DOpcodeSystemSync::s_opNames[8] = {
0, 0, "clrex", 0, "dsb", "dmb", "isb", 0
};
@@ -1193,6 +1231,30 @@
return m_formatBuffer;
}
+const char* const A64DOpcodeLoadStoreAuthenticated::s_opNames[2] = {
+ "ldraa", "ldrab"
+};
+
+const char* A64DOpcodeLoadStoreAuthenticated::format()
+{
+ appendInstructionName(opName());
+ appendRegisterName(rt());
+ appendSeparator();
+ appendCharacter('[');
+ appendSPOrRegisterName(rn());
+
+ if (wBit() || immediate10()) {
+ appendSeparator();
+ appendSignedImmediate(immediate10() << size());
+ }
+ appendCharacter(']');
+
+ if (wBit())
+ appendCharacter('!');
+
+ return m_formatBuffer;
+}
+
const char* A64DOpcodeLoadStoreRegisterPair::opName()
{
if (!vBit() && lBit() && size() == 0x1)
@@ -1452,10 +1514,40 @@
}
const char* const A64DOpcodeUnconditionalBranchRegister::s_opNames[8] = { "br", "blr", "ret", "", "eret", "drps", "", "" };
+const char* const A64DOpcodeUnconditionalBranchRegister::s_AuthOpNames[20] = {
+ "braaz", "brabz", "blraaz", "blrabz", "retaa", "retab", 0, 0,
+ "eretaa", "eretab", 0, 0, 0, 0, 0, 0,
+ "braa", "brab", "blraa", "blrab"
+};
+const char* A64DOpcodeUnconditionalBranchRegister::authOpName()
+{
+ unsigned opCode = authOpCode();
+ if (opCode >= 20)
+ return 0;
+ return s_AuthOpNames[opCode];
+}
+
const char* A64DOpcodeUnconditionalBranchRegister::format()
{
unsigned opcValue = opc();
+ if (op2() == 0x1f && (op3() & 0x3e) == 0x2) {
+ const char* opName = authOpName();
+ if (!opName)
+ return A64DOpcode::format();
+ if (rn() != 0x1f && (opcValue == 0x2 || opcValue == 0x4))
+ return A64DOpcode::format();
+
+ appendInstructionName(opName);
+ if ((opcValue & 0x7) <= 0x1)
+ appendRegisterName(rn());
+ if (opcValue & 0x8) {
+ appendSeparator();
+ appendRegisterName(rm());
+ }
+
+ return m_formatBuffer;
+ }
if (opcValue == 3 || opcValue > 5)
return A64DOpcode::format();
if (((opcValue & 0xe) == 0x4) && rn() != 0x1f)
Modified: trunk/Source/_javascript_Core/disassembler/ARM64/A64DOpcode.h (246146 => 246147)
--- trunk/Source/_javascript_Core/disassembler/ARM64/A64DOpcode.h 2019-06-06 08:58:04 UTC (rev 246146)
+++ trunk/Source/_javascript_Core/disassembler/ARM64/A64DOpcode.h 2019-06-06 09:31:40 UTC (rev 246147)
@@ -340,6 +340,7 @@
class A64DOpcodeDataProcessing1Source : public A64DOpcode {
private:
static const char* const s_opNames[8];
+ static const char* const s_pacAutOpNames[18];
public:
static const uint32_t mask = 0x5fe00000;
@@ -358,7 +359,7 @@
class A64DOpcodeDataProcessing2Source : public A64DOpcode {
private:
- static const char* const s_opNames[8];
+ static const char* const s_opNames[16];
public:
static const uint32_t mask = 0x5fe00000;
@@ -371,7 +372,7 @@
const char* opName() { return s_opNames[opNameIndex()]; }
unsigned sBit() { return (m_opcode >> 29) & 0x1; }
unsigned opCode() { return (m_opcode >> 10) & 0x3f; }
- unsigned opNameIndex() { return ((m_opcode >> 11) & 0x4) | ((m_opcode >> 10) & 0x3); }
+ unsigned opNameIndex() { return (m_opcode >> 10) & 0xf; }
};
class A64DOpcodeDataProcessing3Source : public A64DOpcode {
@@ -571,7 +572,7 @@
class A64DOpcodeHint : public A64DOpcodeSystem {
private:
- static const char* const s_opNames[6];
+ static const char* const s_opNames[32];
public:
static const uint32_t mask = 0xfffff01f;
@@ -581,7 +582,7 @@
const char* format();
- const char* opName() { return immediate7() <= 5 ? s_opNames[immediate7()] : "hint"; }
+ const char* opName();
unsigned immediate7() { return (m_opcode >> 5) & 0x7f; }
};
@@ -683,6 +684,32 @@
int sBit() { return (m_opcode >> 12) & 0x1; }
};
+class A64DOpcodeLoadStoreAuthenticated : public A64DOpcodeLoadStore {
+private:
+ static const char* const s_opNames[2];
+
+protected:
+ const char* opName()
+ {
+ return s_opNames[opNumber()];
+ }
+
+public:
+ static const uint32_t mask = 0xff200400;
+ static const uint32_t pattern = 0xf8200400;
+
+ DEFINE_STATIC_FORMAT(A64DOpcodeLoadStoreAuthenticated, thisObj);
+
+ const char* format();
+
+ unsigned opNum() { return mBit(); }
+ unsigned mBit() { return (m_opcode >> 23) & 0x1; }
+ unsigned sBit() { return (m_opcode >> 22) & 0x1; }
+ unsigned wBit() { return (m_opcode >> 11) & 0x1; }
+ int immediate10() { return (sBit() << 9) | ((m_opcode >> 12) & 0x1ff); }
+
+};
+
class A64DOpcodeLoadStoreRegisterPair : public A64DOpcodeLoadStore {
public:
static const uint32_t mask = 0x3a000000;
@@ -806,9 +833,10 @@
class A64DOpcodeUnconditionalBranchRegister : public A64DOpcode {
private:
static const char* const s_opNames[8];
+ static const char* const s_AuthOpNames[20];
public:
- static const uint32_t mask = 0xfe1ffc1f;
+ static const uint32_t mask = 0xfe1f0000;
static const uint32_t pattern = 0xd61f0000;
DEFINE_STATIC_FORMAT(A64DOpcodeUnconditionalBranchRegister, thisObj);
@@ -816,7 +844,14 @@
const char* format();
const char* opName() { return s_opNames[opc()]; }
+ const char* authOpName();
unsigned opc() { return (m_opcode >> 21) & 0xf; }
+ unsigned authOpCode() {return (opc() << 1) | mBit(); }
+ unsigned op2() { return (m_opcode >> 16) & 0x1f; }
+ unsigned op3() { return (m_opcode >> 10) & 0x3f; }
+ unsigned op4() { return m_opcode & 0xf; }
+ unsigned mBit() { return (m_opcode >> 10) & 1; }
+ unsigned rm() { return rd(); }
};
} } // namespace JSC::ARM64Disassembler
_______________________________________________ webkit-changes mailing list [email protected] https://lists.webkit.org/mailman/listinfo/webkit-changes
