Title: [283914] trunk/Source/_javascript_Core
- Revision
- 283914
- Author
- [email protected]
- Date
- 2021-10-11 11:28:39 -0700 (Mon, 11 Oct 2021)
Log Message
[JSC][ARMv7] Make LLInt CSR save/restore order match the JITs
https://bugs.webkit.org/show_bug.cgi?id=231517
Patch by Geza Lore <[email protected]> on 2021-10-11
Reviewed by Saam Barati.
Since the new unlinked baseline JIT was introduced, the baseline JIT
uses the metadata table GPR the same way as the LLInt does, and relies
on it being in a saved CSR in emit_op_catch. This unearthed an issue
in the order in which LLInt on ARMv7 stores and restores CSRs when
trying to handle exceptions. This patch fixes the mismatch.
* llint/LowLevelInterpreter.asm:
Modified Paths
Diff
Modified: trunk/Source/_javascript_Core/ChangeLog (283913 => 283914)
--- trunk/Source/_javascript_Core/ChangeLog 2021-10-11 18:16:38 UTC (rev 283913)
+++ trunk/Source/_javascript_Core/ChangeLog 2021-10-11 18:28:39 UTC (rev 283914)
@@ -1,3 +1,18 @@
+2021-10-11 Geza Lore <[email protected]>
+
+ [JSC][ARMv7] Make LLInt CSR save/restore order match the JITs
+ https://bugs.webkit.org/show_bug.cgi?id=231517
+
+ Reviewed by Saam Barati.
+
+ Since the new unlinked baseline JIT was introduced, the baseline JIT
+ uses the metadata table GPR the same way as the LLInt does, and relies
+ on it being in a saved CSR in emit_op_catch. This unearthed an issue
+ in the order in which LLInt on ARMv7 stores and restores CSRs when
+ trying to handle exceptions. This patch fixes the mismatch.
+
+ * llint/LowLevelInterpreter.asm:
+
2021-10-11 Alex Christensen <[email protected]>
Prepare to switch from WTF::Variant to std::variant
Modified: trunk/Source/_javascript_Core/llint/LowLevelInterpreter.asm (283913 => 283914)
--- trunk/Source/_javascript_Core/llint/LowLevelInterpreter.asm 2021-10-11 18:16:38 UTC (rev 283913)
+++ trunk/Source/_javascript_Core/llint/LowLevelInterpreter.asm 2021-10-11 18:28:39 UTC (rev 283914)
@@ -934,7 +934,12 @@
storeq csr4, 32[entryFrame]
storeq csr5, 40[entryFrame]
storeq csr6, 48[entryFrame]
- elsif ARMv7 or MIPS
+ # To understand why ARMv7 and MIPS differ in store order,
+ # see comment in preserveCalleeSavesUsedByLLInt
+ elsif ARMv7
+ storep csr1, [entryFrame]
+ storep csr0, 4[entryFrame]
+ elsif MIPS
storep csr0, [entryFrame]
storep csr1, 4[entryFrame]
elsif RISCV64
@@ -1010,7 +1015,12 @@
loadq 32[temp], csr4
loadq 40[temp], csr5
loadq 48[temp], csr6
- elsif ARMv7 or MIPS
+ # To understand why ARMv7 and MIPS differ in restore order,
+ # see comment in preserveCalleeSavesUsedByLLInt
+ elsif ARMv7
+ loadp [temp], csr1
+ loadp 4[temp], csr0
+ elsif MIPS
loadp [temp], csr0
loadp 4[temp], csr1
elsif RISCV64
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