[webkit-changes] [287513] trunk/Source/JavaScriptCore

Sun, 02 Jan 2022 02:33:00 -0800

Title: [287513] trunk/Source/_javascript_Core
Revision
287513
Author
[email protected]
Date
2022-01-02 02:32:22 -0800 (Sun, 02 Jan 2022)

Log Message

[RISCV64] Make DFG, FTL, B3, WASM buildable on CPU(RISCV64)
https://bugs.webkit.org/show_bug.cgi?id=234775

Patch by Zan Dobersek <[email protected]> on 2022-01-02
Reviewed by Yusuke Suzuki.

Enable building DFG, FTL, B3 and WASM subsystems on 64-bit RISC-V.
Necessary guards and missing bits are added to make things buildable,
but actual enabling of these features at build-time is left for later.
Even when enabled at build-time in the future, there'll likey be open
issues that will require disabling different features at run-time.

MacroAssemblerRISCV64::setCarry() no-op method is added for now. Carry
flag retrieval isn't exactly possible on RISC-V, so the uses of it will
have to be addressed some other way.

The patchpointScratchRegister value is defined for CPU(RISCV64). As
on ARM64, the value matches MacroAssemblerRISCV64::dataTempRegister.

In B3, we follow ARM64 in the pinned extended-offset-address use and
stack argument lowering.

in WASM, we can again mirror ARM64 around LLInt callee registers and
slots as well as executing the epilogue of a OSR-entry callee.

* assembler/MacroAssembler.h: Provide lea64() for CPU(RISCV64) as well.
* assembler/MacroAssemblerRISCV64.h:
* b3/B3Common.cpp:
(JSC::B3::pinnedExtendedOffsetAddrRegister):
* b3/air/AirLowerStackArgs.cpp:
(JSC::B3::Air::lowerStackArgs):
* jit/GPRInfo.h:
* wasm/WasmCallee.cpp:
(JSC::Wasm::LLIntCallee::calleeSaveRegisters):
* wasm/WasmLLIntPlan.cpp:
(JSC::Wasm::LLIntPlan::didCompleteCompilation):
* wasm/WasmOperations.cpp:
(JSC::Wasm::doOSREntry):

Modified Paths

Diff

Modified: trunk/Source/_javascript_Core/ChangeLog (287512 => 287513)


--- trunk/Source/_javascript_Core/ChangeLog	2022-01-02 09:12:42 UTC (rev 287512)
+++ trunk/Source/_javascript_Core/ChangeLog	2022-01-02 10:32:22 UTC (rev 287513)
@@ -1,5 +1,45 @@
 2022-01-02  Zan Dobersek  <[email protected]>
 
+        [RISCV64] Make DFG, FTL, B3, WASM buildable on CPU(RISCV64)
+        https://bugs.webkit.org/show_bug.cgi?id=234775
+
+        Reviewed by Yusuke Suzuki.
+
+        Enable building DFG, FTL, B3 and WASM subsystems on 64-bit RISC-V.
+        Necessary guards and missing bits are added to make things buildable,
+        but actual enabling of these features at build-time is left for later.
+        Even when enabled at build-time in the future, there'll likey be open
+        issues that will require disabling different features at run-time.
+
+        MacroAssemblerRISCV64::setCarry() no-op method is added for now. Carry
+        flag retrieval isn't exactly possible on RISC-V, so the uses of it will
+        have to be addressed some other way.
+
+        The patchpointScratchRegister value is defined for CPU(RISCV64). As
+        on ARM64, the value matches MacroAssemblerRISCV64::dataTempRegister.
+
+        In B3, we follow ARM64 in the pinned extended-offset-address use and
+        stack argument lowering.
+
+        in WASM, we can again mirror ARM64 around LLInt callee registers and
+        slots as well as executing the epilogue of a OSR-entry callee.
+
+        * assembler/MacroAssembler.h: Provide lea64() for CPU(RISCV64) as well.
+        * assembler/MacroAssemblerRISCV64.h:
+        * b3/B3Common.cpp:
+        (JSC::B3::pinnedExtendedOffsetAddrRegister):
+        * b3/air/AirLowerStackArgs.cpp:
+        (JSC::B3::Air::lowerStackArgs):
+        * jit/GPRInfo.h:
+        * wasm/WasmCallee.cpp:
+        (JSC::Wasm::LLIntCallee::calleeSaveRegisters):
+        * wasm/WasmLLIntPlan.cpp:
+        (JSC::Wasm::LLIntPlan::didCompleteCompilation):
+        * wasm/WasmOperations.cpp:
+        (JSC::Wasm::doOSREntry):
+
+2022-01-02  Zan Dobersek  <[email protected]>
+
         [RISCV64] Enable building LLInt WebAssembly via the riscv64 offlineasm backend
         https://bugs.webkit.org/show_bug.cgi?id=234776

Modified: trunk/Source/_javascript_Core/assembler/MacroAssembler.h (287512 => 287513)


--- trunk/Source/_javascript_Core/assembler/MacroAssembler.h	2022-01-02 09:12:42 UTC (rev 287512)
+++ trunk/Source/_javascript_Core/assembler/MacroAssembler.h	2022-01-02 10:32:22 UTC (rev 287513)
@@ -1459,7 +1459,7 @@
         add32(TrustedImm32(address.offset), address.base, dest);
     }
 
-#if CPU(X86_64) || CPU(ARM64)
+#if CPU(X86_64) || CPU(ARM64) || CPU(RISCV64)
     void lea64(Address address, RegisterID dest)
     {
         add64(TrustedImm32(address.offset), address.base, dest);

Modified: trunk/Source/_javascript_Core/assembler/MacroAssemblerRISCV64.h (287512 => 287513)


--- trunk/Source/_javascript_Core/assembler/MacroAssemblerRISCV64.h	2022-01-02 09:12:42 UTC (rev 287512)
+++ trunk/Source/_javascript_Core/assembler/MacroAssemblerRISCV64.h	2022-01-02 10:32:22 UTC (rev 287513)
@@ -1829,6 +1829,8 @@
         testFinalize(cond, dest, dest);
     }
 
+    MACRO_ASSEMBLER_RISCV64_TEMPLATED_NOOP_METHOD(setCarry);
+
     Jump branch8(RelationalCondition cond, Address address, TrustedImm32 imm)
     {
         auto temp = temps<Data, Memory>();

Modified: trunk/Source/_javascript_Core/b3/B3Common.cpp (287512 => 287513)


--- trunk/Source/_javascript_Core/b3/B3Common.cpp	2022-01-02 09:12:42 UTC (rev 287512)
+++ trunk/Source/_javascript_Core/b3/B3Common.cpp	2022-01-02 10:32:22 UTC (rev 287513)
@@ -72,7 +72,7 @@
 
 std::optional<GPRReg> pinnedExtendedOffsetAddrRegister()
 {
-#if CPU(ARM64)
+#if CPU(ARM64) || CPU(RISCV64)
     return MacroAssembler::dataTempRegister;
 #elif CPU(X86_64)
     return std::nullopt;

Modified: trunk/Source/_javascript_Core/b3/air/AirLowerStackArgs.cpp (287512 => 287513)


--- trunk/Source/_javascript_Core/b3/air/AirLowerStackArgs.cpp	2022-01-02 09:12:42 UTC (rev 287512)
+++ trunk/Source/_javascript_Core/b3/air/AirLowerStackArgs.cpp	2022-01-02 10:32:22 UTC (rev 287513)
@@ -127,7 +127,7 @@
                         result = Arg::addr(Air::Tmp(MacroAssembler::stackPointerRegister), offsetFromSP);
                         if (result.isValidForm(width))
                             return result;
-#if CPU(ARM64)
+#if CPU(ARM64) || CPU(RISCV64)
                         ASSERT(pinnedExtendedOffsetAddrRegister());
                         Air::Tmp tmp = Air::Tmp(*pinnedExtendedOffsetAddrRegister());
 
@@ -157,7 +157,7 @@
                             RELEASE_ASSERT(slot->byteSize() == 8);
                             RELEASE_ASSERT(width == Width32);
 
-#if CPU(ARM64)
+#if CPU(ARM64) || CPU(RISCV64)
                             Air::Opcode storeOpcode = Store32;
                             Air::Arg::Kind operandKind = Arg::ZeroReg;
                             Air::Arg operand = Arg::zeroReg();

Modified: trunk/Source/_javascript_Core/jit/GPRInfo.h (287512 => 287513)


--- trunk/Source/_javascript_Core/jit/GPRInfo.h	2022-01-02 09:12:42 UTC (rev 287512)
+++ trunk/Source/_javascript_Core/jit/GPRInfo.h	2022-01-02 10:32:22 UTC (rev 287513)
@@ -879,6 +879,8 @@
     static constexpr GPRReg wasmScratchGPR0 = RISCV64Registers::x6; // regT9
     static constexpr GPRReg wasmScratchGPR1 = RISCV64Registers::x7; // regT10
 
+    static constexpr GPRReg patchpointScratchRegister = RISCV64Registers::x30; // Should match dataTempRegister
+
     static GPRReg toRegister(unsigned index)
     {
         ASSERT(index < numberOfRegisters);

Modified: trunk/Source/_javascript_Core/wasm/WasmCallee.cpp (287512 => 287513)


--- trunk/Source/_javascript_Core/wasm/WasmCallee.cpp	2022-01-02 09:12:42 UTC (rev 287512)
+++ trunk/Source/_javascript_Core/wasm/WasmCallee.cpp	2022-01-02 10:32:22 UTC (rev 287513)
@@ -128,7 +128,7 @@
         registers.set(GPRInfo::regCS0); // Wasm::Instance
 #if CPU(X86_64)
         registers.set(GPRInfo::regCS2); // PB
-#elif CPU(ARM64)
+#elif CPU(ARM64) || CPU(RISCV64)
         registers.set(GPRInfo::regCS7); // PB
 #else
 #error Unsupported architecture.

Modified: trunk/Source/_javascript_Core/wasm/WasmLLIntPlan.cpp (287512 => 287513)


--- trunk/Source/_javascript_Core/wasm/WasmLLIntPlan.cpp	2022-01-02 09:12:42 UTC (rev 287512)
+++ trunk/Source/_javascript_Core/wasm/WasmLLIntPlan.cpp	2022-01-02 10:32:22 UTC (rev 287513)
@@ -119,7 +119,7 @@
             entrypoints[i] = jit.label();
 #if CPU(X86_64)
             CCallHelpers::Address calleeSlot(CCallHelpers::stackPointerRegister, CallFrameSlot::callee * static_cast<int>(sizeof(Register)) - sizeof(CPURegister));
-#elif CPU(ARM64)
+#elif CPU(ARM64) || CPU(RISCV64)
             CCallHelpers::Address calleeSlot(CCallHelpers::stackPointerRegister, CallFrameSlot::callee * static_cast<int>(sizeof(Register)) - sizeof(CallerFrameAndPC));
 #else
 #error Unsupported architecture.

Modified: trunk/Source/_javascript_Core/wasm/WasmOperations.cpp (287512 => 287513)


--- trunk/Source/_javascript_Core/wasm/WasmOperations.cpp	2022-01-02 09:12:42 UTC (rev 287512)
+++ trunk/Source/_javascript_Core/wasm/WasmOperations.cpp	2022-01-02 10:32:22 UTC (rev 287513)
@@ -204,6 +204,13 @@
     // LR needs to be untagged since OSR entry function prologue will tag it with SP. This is similar to tail-call.
     context.gpr(ARM64Registers::lr) = bitwise_cast<UCPURegister>(untagCodePtrWithStackPointerForJITCall(context.gpr<void*>(ARM64Registers::lr), context.sp()));
 #endif
+#elif CPU(RISCV64)
+    // move(framePointerRegister, stackPointerRegister);
+    // popPair(framePointerRegister, linkRegister);
+    context.fp() = bitwise_cast<UCPURegister*>(*framePointer);
+    context.gpr(RISCV64Registers::ra) = bitwise_cast<UCPURegister>(*(framePointer + 1));
+    context.sp() = framePointer + 2;
+    static_assert(AssemblyHelpers::prologueStackPointerDelta() == sizeof(void*) * 2);
 #else
 #error Unsupported architecture.
 #endif

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