[webkit-changes] [293759] trunk/Source/JavaScriptCore

Tue, 03 May 2022 23:15:29 -0700

Title: [293759] trunk/Source/_javascript_Core
Revision
293759
Author
[email protected]
Date
2022-05-03 23:14:20 -0700 (Tue, 03 May 2022)

Log Message

[RISCV64] Implement MacroAssemblerRISCV64 move-conditionally methods
https://bugs.webkit.org/show_bug.cgi?id=239998

Reviewed by Yusuke Suzuki.

Provide implementations for the variants of the move-conditionally
operation in MacroAssemblerRISCV64. These are true macro operations,
often requiring scratch registers and branches to implement the
behavior since the RISC-V ISA doesn't provide appropriate instructions
out-of-the-box.

Test cases in testmasm are also enabled, including some additional
guards to avoid unused-variable warnings at build-time.

* assembler/MacroAssemblerRISCV64.h:
(JSC::MacroAssemblerRISCV64::moveConditionally32):
(JSC::MacroAssemblerRISCV64::moveConditionally64):
(JSC::MacroAssemblerRISCV64::moveConditionallyFloat):
(JSC::MacroAssemblerRISCV64::moveConditionallyDouble):
(JSC::MacroAssemblerRISCV64::moveConditionallyTest32):
(JSC::MacroAssemblerRISCV64::moveConditionallyTest64):
(JSC::MacroAssemblerRISCV64::moveDoubleConditionally32):
(JSC::MacroAssemblerRISCV64::moveDoubleConditionally64):
(JSC::MacroAssemblerRISCV64::moveDoubleConditionallyFloat):
(JSC::MacroAssemblerRISCV64::moveDoubleConditionallyDouble):
(JSC::MacroAssemblerRISCV64::moveDoubleConditionallyTest32):
(JSC::MacroAssemblerRISCV64::moveDoubleConditionallyTest64):
(JSC::MacroAssemblerRISCV64::branchForMoveConditionally):
* assembler/testmasm.cpp:
(JSC::testProbeModifiesStackPointer):
(JSC::testProbeModifiesStackValues):

Modified Paths

Diff

Modified: trunk/Source/_javascript_Core/ChangeLog (293758 => 293759)


--- trunk/Source/_javascript_Core/ChangeLog	2022-05-04 03:17:09 UTC (rev 293758)
+++ trunk/Source/_javascript_Core/ChangeLog	2022-05-04 06:14:20 UTC (rev 293759)
@@ -1,3 +1,37 @@
+2022-05-03  Zan Dobersek  <[email protected]>
+
+        [RISCV64] Implement MacroAssemblerRISCV64 move-conditionally methods
+        https://bugs.webkit.org/show_bug.cgi?id=239998
+
+        Reviewed by Yusuke Suzuki.
+
+        Provide implementations for the variants of the move-conditionally
+        operation in MacroAssemblerRISCV64. These are true macro operations,
+        often requiring scratch registers and branches to implement the
+        behavior since the RISC-V ISA doesn't provide appropriate instructions
+        out-of-the-box.
+
+        Test cases in testmasm are also enabled, including some additional
+        guards to avoid unused-variable warnings at build-time.
+
+        * assembler/MacroAssemblerRISCV64.h:
+        (JSC::MacroAssemblerRISCV64::moveConditionally32):
+        (JSC::MacroAssemblerRISCV64::moveConditionally64):
+        (JSC::MacroAssemblerRISCV64::moveConditionallyFloat):
+        (JSC::MacroAssemblerRISCV64::moveConditionallyDouble):
+        (JSC::MacroAssemblerRISCV64::moveConditionallyTest32):
+        (JSC::MacroAssemblerRISCV64::moveConditionallyTest64):
+        (JSC::MacroAssemblerRISCV64::moveDoubleConditionally32):
+        (JSC::MacroAssemblerRISCV64::moveDoubleConditionally64):
+        (JSC::MacroAssemblerRISCV64::moveDoubleConditionallyFloat):
+        (JSC::MacroAssemblerRISCV64::moveDoubleConditionallyDouble):
+        (JSC::MacroAssemblerRISCV64::moveDoubleConditionallyTest32):
+        (JSC::MacroAssemblerRISCV64::moveDoubleConditionallyTest64):
+        (JSC::MacroAssemblerRISCV64::branchForMoveConditionally):
+        * assembler/testmasm.cpp:
+        (JSC::testProbeModifiesStackPointer):
+        (JSC::testProbeModifiesStackValues):
+
 2022-05-03  Yusuke Suzuki  <[email protected]>
 
         [JSC] Extend Structure heap size from 1GB to 4GB

Modified: trunk/Source/_javascript_Core/assembler/MacroAssemblerRISCV64.h (293758 => 293759)


--- trunk/Source/_javascript_Core/assembler/MacroAssemblerRISCV64.h	2022-05-04 03:17:09 UTC (rev 293758)
+++ trunk/Source/_javascript_Core/assembler/MacroAssemblerRISCV64.h	2022-05-04 06:14:20 UTC (rev 293759)
@@ -3435,19 +3435,285 @@
         return failure;
     }
 
-    MACRO_ASSEMBLER_RISCV64_TEMPLATED_NOOP_METHOD(moveConditionally32);
-    MACRO_ASSEMBLER_RISCV64_TEMPLATED_NOOP_METHOD(moveConditionally64);
-    MACRO_ASSEMBLER_RISCV64_TEMPLATED_NOOP_METHOD(moveConditionallyFloat);
-    MACRO_ASSEMBLER_RISCV64_TEMPLATED_NOOP_METHOD(moveConditionallyDouble);
-    MACRO_ASSEMBLER_RISCV64_TEMPLATED_NOOP_METHOD(moveConditionallyTest32);
-    MACRO_ASSEMBLER_RISCV64_TEMPLATED_NOOP_METHOD(moveConditionallyTest64);
-    MACRO_ASSEMBLER_RISCV64_TEMPLATED_NOOP_METHOD(moveDoubleConditionally32);
-    MACRO_ASSEMBLER_RISCV64_TEMPLATED_NOOP_METHOD(moveDoubleConditionally64);
-    MACRO_ASSEMBLER_RISCV64_TEMPLATED_NOOP_METHOD(moveDoubleConditionallyFloat);
-    MACRO_ASSEMBLER_RISCV64_TEMPLATED_NOOP_METHOD(moveDoubleConditionallyDouble);
-    MACRO_ASSEMBLER_RISCV64_TEMPLATED_NOOP_METHOD(moveDoubleConditionallyTest32);
-    MACRO_ASSEMBLER_RISCV64_TEMPLATED_NOOP_METHOD(moveDoubleConditionallyTest64);
+    void moveConditionally32(RelationalCondition cond, RegisterID lhs, RegisterID rhs, RegisterID src, RegisterID dest)
+    {
+        auto temp = temps<Data, Memory>();
+        m_assembler.signExtend<32>(temp.data(), lhs);
+        m_assembler.signExtend<32>(temp.memory(), rhs);
 
+        branchForMoveConditionally(invert(cond), temp.data(), temp.memory(), Imm::B<8>());
+        m_assembler.addiInsn(dest, src, Imm::I<0>());
+    }
+
+    void moveConditionally32(RelationalCondition cond, RegisterID lhs, RegisterID rhs, RegisterID trueSrc, RegisterID falseSrc, RegisterID dest)
+    {
+        auto temp = temps<Data, Memory>();
+        m_assembler.signExtend<32>(temp.data(), lhs);
+        m_assembler.signExtend<32>(temp.memory(), rhs);
+
+        branchForMoveConditionally(invert(cond), temp.data(), temp.memory(), Imm::B<12>());
+        m_assembler.addiInsn(dest, trueSrc, Imm::I<0>());
+        m_assembler.jalInsn(RISCV64Registers::zero, Imm::J<8>());
+        m_assembler.addiInsn(dest, falseSrc, Imm::I<0>());
+    }
+
+    void moveConditionally32(RelationalCondition cond, RegisterID lhs, TrustedImm32 imm, RegisterID trueSrc, RegisterID falseSrc, RegisterID dest)
+    {
+        auto temp = temps<Data, Memory>();
+        m_assembler.signExtend<32>(temp.data(), lhs);
+        loadImmediate(imm, temp.memory());
+
+        branchForMoveConditionally(invert(cond), temp.data(), temp.memory(), Imm::B<12>());
+        m_assembler.addiInsn(dest, trueSrc, Imm::I<0>());
+        m_assembler.jalInsn(RISCV64Registers::zero, Imm::J<8>());
+        m_assembler.addiInsn(dest, falseSrc, Imm::I<0>());
+    }
+
+    void moveConditionally64(RelationalCondition cond, RegisterID lhs, RegisterID rhs, RegisterID src, RegisterID dest)
+    {
+        branchForMoveConditionally(invert(cond), lhs, rhs, Imm::B<8>());
+        m_assembler.addiInsn(dest, src, Imm::I<0>());
+    }
+
+    void moveConditionally64(RelationalCondition cond, RegisterID lhs, RegisterID rhs, RegisterID trueSrc, RegisterID falseSrc, RegisterID dest)
+    {
+        branchForMoveConditionally(invert(cond), lhs, rhs, Imm::B<12>());
+        m_assembler.addiInsn(dest, trueSrc, Imm::I<0>());
+        m_assembler.jalInsn(RISCV64Registers::zero, Imm::J<8>());
+        m_assembler.addiInsn(dest, falseSrc, Imm::I<0>());
+    }
+
+    void moveConditionally64(RelationalCondition cond, RegisterID lhs, TrustedImm32 imm, RegisterID trueSrc, RegisterID falseSrc, RegisterID dest)
+    {
+        auto temp = temps<Data>();
+        loadImmediate(imm, temp.data());
+        branchForMoveConditionally(invert(cond), lhs, temp.data(), Imm::B<12>());
+        m_assembler.addiInsn(dest, trueSrc, Imm::I<0>());
+        m_assembler.jalInsn(RISCV64Registers::zero, Imm::J<8>());
+        m_assembler.addiInsn(dest, falseSrc, Imm::I<0>());
+    }
+
+    void moveConditionallyFloat(DoubleCondition cond, FPRegisterID lhs, FPRegisterID rhs, RegisterID src, RegisterID dest)
+    {
+        Jump invcondBranch = branchFP<32, true>(cond, lhs, rhs);
+        m_assembler.addiInsn(dest, src, Imm::I<0>());
+        invcondBranch.link(this);
+    }
+
+    void moveConditionallyFloat(DoubleCondition cond, FPRegisterID lhs, FPRegisterID rhs, RegisterID trueSrc, RegisterID falseSrc, RegisterID dest)
+    {
+        Jump invcondBranch = branchFP<32, true>(cond, lhs, rhs);
+        m_assembler.addiInsn(dest, trueSrc, Imm::I<0>());
+        Jump end = jump();
+        invcondBranch.link(this);
+        m_assembler.addiInsn(dest, falseSrc, Imm::I<0>());
+        end.link(this);
+    }
+
+    void moveConditionallyDouble(DoubleCondition cond, FPRegisterID lhs, FPRegisterID rhs, RegisterID src, RegisterID dest)
+    {
+        Jump invcondBranch = branchFP<64, true>(cond, lhs, rhs);
+        m_assembler.addiInsn(dest, src, Imm::I<0>());
+        invcondBranch.link(this);
+    }
+
+    void moveConditionallyDouble(DoubleCondition cond, FPRegisterID lhs, FPRegisterID rhs, RegisterID trueSrc, RegisterID falseSrc, RegisterID dest)
+    {
+        Jump invcondBranch = branchFP<64, true>(cond, lhs, rhs);
+        m_assembler.addiInsn(dest, trueSrc, Imm::I<0>());
+        Jump end = jump();
+        invcondBranch.link(this);
+        m_assembler.addiInsn(dest, falseSrc, Imm::I<0>());
+        end.link(this);
+    }
+
+    void moveConditionallyTest32(ResultCondition cond, RegisterID value, RegisterID mask, RegisterID src, RegisterID dest)
+    {
+        auto temp = temps<Data>();
+        m_assembler.andInsn(temp.data(), value, mask);
+        m_assembler.signExtend<32>(temp.data());
+        testFinalize(cond, temp.data(), temp.data());
+
+        m_assembler.beqInsn(temp.data(), RISCV64Registers::zero, Imm::B<8>());
+        m_assembler.addiInsn(dest, src, Imm::I<0>());
+    }
+
+    void moveConditionallyTest32(ResultCondition cond, RegisterID value, RegisterID mask, RegisterID trueSrc, RegisterID falseSrc, RegisterID dest)
+    {
+        auto temp = temps<Data>();
+        m_assembler.andInsn(temp.data(), value, mask);
+        m_assembler.signExtend<32>(temp.data());
+        testFinalize(cond, temp.data(), temp.data());
+
+        m_assembler.beqInsn(temp.data(), RISCV64Registers::zero, Imm::B<12>());
+        m_assembler.addiInsn(dest, trueSrc, Imm::I<0>());
+        m_assembler.jalInsn(RISCV64Registers::zero, Imm::J<8>());
+        m_assembler.addiInsn(dest, falseSrc, Imm::I<0>());
+    }
+
+    void moveConditionallyTest32(ResultCondition cond, RegisterID value, TrustedImm32 mask, RegisterID trueSrc, RegisterID falseSrc, RegisterID dest)
+    {
+        auto temp = temps<Data>();
+        loadImmediate(mask, temp.data());
+        m_assembler.andInsn(temp.data(), value, temp.data());
+        m_assembler.signExtend<32>(temp.data());
+        testFinalize(cond, temp.data(), temp.data());
+
+        m_assembler.beqInsn(temp.data(), RISCV64Registers::zero, Imm::B<12>());
+        m_assembler.addiInsn(dest, trueSrc, Imm::I<0>());
+        m_assembler.jalInsn(RISCV64Registers::zero, Imm::J<8>());
+        m_assembler.addiInsn(dest, falseSrc, Imm::I<0>());
+    }
+
+    void moveConditionallyTest64(ResultCondition cond, RegisterID value, RegisterID mask, RegisterID src, RegisterID dest)
+    {
+        auto temp = temps<Data>();
+        m_assembler.andInsn(temp.data(), value, mask);
+        testFinalize(cond, temp.data(), temp.data());
+
+        m_assembler.beqInsn(temp.data(), RISCV64Registers::zero, Imm::B<8>());
+        m_assembler.addiInsn(dest, src, Imm::I<0>());
+    }
+
+    void moveConditionallyTest64(ResultCondition cond, RegisterID value, RegisterID mask, RegisterID trueSrc, RegisterID falseSrc, RegisterID dest)
+    {
+        auto temp = temps<Data>();
+        m_assembler.andInsn(temp.data(), value, mask);
+        testFinalize(cond, temp.data(), temp.data());
+
+        m_assembler.beqInsn(temp.data(), RISCV64Registers::zero, Imm::B<12>());
+        m_assembler.addiInsn(dest, trueSrc, Imm::I<0>());
+        m_assembler.jalInsn(RISCV64Registers::zero, Imm::J<8>());
+        m_assembler.addiInsn(dest, falseSrc, Imm::I<0>());
+    }
+
+    void moveConditionallyTest64(ResultCondition cond, RegisterID value, TrustedImm32 mask, RegisterID trueSrc, RegisterID falseSrc, RegisterID dest)
+    {
+        auto temp = temps<Data>();
+        loadImmediate(mask, temp.data());
+        m_assembler.andInsn(temp.data(), value, temp.data());
+        testFinalize(cond, temp.data(), temp.data());
+
+        m_assembler.beqInsn(temp.data(), RISCV64Registers::zero, Imm::B<12>());
+        m_assembler.addiInsn(dest, trueSrc, Imm::I<0>());
+        m_assembler.jalInsn(RISCV64Registers::zero, Imm::J<8>());
+        m_assembler.addiInsn(dest, falseSrc, Imm::I<0>());
+    }
+
+    void moveDoubleConditionally32(RelationalCondition cond, RegisterID lhs, RegisterID rhs, FPRegisterID trueSrc, FPRegisterID falseSrc, FPRegisterID dest)
+    {
+        auto temp = temps<Data, Memory>();
+        m_assembler.signExtend<32>(temp.data(), lhs);
+        m_assembler.signExtend<32>(temp.memory(), rhs);
+
+        branchForMoveConditionally(invert(cond), temp.data(), temp.memory(), Imm::B<12>());
+        m_assembler.fsgnjInsn<64>(dest, trueSrc, trueSrc);
+        m_assembler.jalInsn(RISCV64Registers::zero, Imm::J<8>());
+        m_assembler.fsgnjInsn<64>(dest, falseSrc, falseSrc);
+    }
+
+    void moveDoubleConditionally32(RelationalCondition cond, RegisterID lhs, TrustedImm32 imm, FPRegisterID trueSrc, FPRegisterID falseSrc, FPRegisterID dest)
+    {
+        auto temp = temps<Data, Memory>();
+        m_assembler.signExtend<32>(temp.data(), lhs);
+        loadImmediate(imm, temp.memory());
+
+        branchForMoveConditionally(invert(cond), temp.data(), temp.memory(), Imm::B<12>());
+        m_assembler.fsgnjInsn<64>(dest, trueSrc, trueSrc);
+        m_assembler.jalInsn(RISCV64Registers::zero, Imm::J<8>());
+        m_assembler.fsgnjInsn<64>(dest, falseSrc, falseSrc);
+    }
+
+    void moveDoubleConditionally64(RelationalCondition cond, RegisterID lhs, RegisterID rhs, FPRegisterID trueSrc, FPRegisterID falseSrc, FPRegisterID dest)
+    {
+        branchForMoveConditionally(invert(cond), lhs, rhs, Imm::B<12>());
+        m_assembler.fsgnjInsn<64>(dest, trueSrc, trueSrc);
+        m_assembler.jalInsn(RISCV64Registers::zero, Imm::J<8>());
+        m_assembler.fsgnjInsn<64>(dest, falseSrc, falseSrc);
+    }
+
+    void moveDoubleConditionally64(RelationalCondition cond, RegisterID lhs, TrustedImm32 imm, FPRegisterID trueSrc, FPRegisterID falseSrc, FPRegisterID dest)
+    {
+        auto temp = temps<Data>();
+        loadImmediate(imm, temp.data());
+        branchForMoveConditionally(invert(cond), lhs, temp.data(), Imm::B<12>());
+        m_assembler.fsgnjInsn<64>(dest, trueSrc, trueSrc);
+        m_assembler.jalInsn(RISCV64Registers::zero, Imm::J<8>());
+        m_assembler.fsgnjInsn<64>(dest, falseSrc, falseSrc);
+    }
+
+    void moveDoubleConditionallyFloat(DoubleCondition cond, FPRegisterID lhs, FPRegisterID rhs, FPRegisterID trueSrc, FPRegisterID falseSrc, FPRegisterID dest)
+    {
+        Jump invcondBranch = branchFP<32, true>(cond, lhs, rhs);
+        m_assembler.fsgnjInsn<64>(dest, trueSrc, trueSrc);
+        Jump end = jump();
+        invcondBranch.link(this);
+        m_assembler.fsgnjInsn<64>(dest, falseSrc, falseSrc);
+        end.link(this);
+    }
+
+    void moveDoubleConditionallyDouble(DoubleCondition cond, FPRegisterID lhs, FPRegisterID rhs, FPRegisterID trueSrc, FPRegisterID falseSrc, FPRegisterID dest)
+    {
+        Jump invcondBranch = branchFP<64, true>(cond, lhs, rhs);
+        m_assembler.fsgnjInsn<64>(dest, trueSrc, trueSrc);
+        Jump end = jump();
+        invcondBranch.link(this);
+        m_assembler.fsgnjInsn<64>(dest, falseSrc, falseSrc);
+        end.link(this);
+    }
+
+    void moveDoubleConditionallyTest32(ResultCondition cond, RegisterID value, RegisterID mask, FPRegisterID trueSrc, FPRegisterID falseSrc, FPRegisterID dest)
+    {
+        auto temp = temps<Data>();
+        m_assembler.andInsn(temp.data(), value, mask);
+        m_assembler.signExtend<32>(temp.data());
+        testFinalize(cond, temp.data(), temp.data());
+
+        m_assembler.beqInsn(temp.data(), RISCV64Registers::zero, Imm::B<12>());
+        m_assembler.fsgnjInsn<64>(dest, trueSrc, trueSrc);
+        m_assembler.jalInsn(RISCV64Registers::zero, Imm::J<8>());
+        m_assembler.fsgnjInsn<64>(dest, falseSrc, falseSrc);
+    }
+
+    void moveDoubleConditionallyTest32(ResultCondition cond, RegisterID value, TrustedImm32 mask, FPRegisterID trueSrc, FPRegisterID falseSrc, FPRegisterID dest)
+    {
+        auto temp = temps<Data>();
+        loadImmediate(mask, temp.data());
+        m_assembler.andInsn(temp.data(), value, temp.data());
+        m_assembler.signExtend<32>(temp.data());
+        testFinalize(cond, temp.data(), temp.data());
+
+        m_assembler.beqInsn(temp.data(), RISCV64Registers::zero, Imm::B<12>());
+        m_assembler.fsgnjInsn<64>(dest, trueSrc, trueSrc);
+        m_assembler.jalInsn(RISCV64Registers::zero, Imm::J<8>());
+        m_assembler.fsgnjInsn<64>(dest, falseSrc, falseSrc);
+    }
+
+    void moveDoubleConditionallyTest64(ResultCondition cond, RegisterID value, RegisterID mask, FPRegisterID trueSrc, FPRegisterID falseSrc, FPRegisterID dest)
+    {
+        auto temp = temps<Data>();
+        m_assembler.andInsn(temp.data(), value, mask);
+        testFinalize(cond, temp.data(), temp.data());
+
+        m_assembler.beqInsn(temp.data(), RISCV64Registers::zero, Imm::B<12>());
+        m_assembler.fsgnjInsn<64>(dest, trueSrc, trueSrc);
+        m_assembler.jalInsn(RISCV64Registers::zero, Imm::J<8>());
+        m_assembler.fsgnjInsn<64>(dest, falseSrc, falseSrc);
+    }
+
+    void moveDoubleConditionallyTest64(ResultCondition cond, RegisterID value, TrustedImm32 mask, FPRegisterID trueSrc, FPRegisterID falseSrc, FPRegisterID dest)
+    {
+        auto temp = temps<Data>();
+        loadImmediate(mask, temp.data());
+        m_assembler.andInsn(temp.data(), value, temp.data());
+        testFinalize(cond, temp.data(), temp.data());
+
+        m_assembler.beqInsn(temp.data(), RISCV64Registers::zero, Imm::B<12>());
+        m_assembler.fsgnjInsn<64>(dest, trueSrc, trueSrc);
+        m_assembler.jalInsn(RISCV64Registers::zero, Imm::J<8>());
+        m_assembler.fsgnjInsn<64>(dest, falseSrc, falseSrc);
+    }
+
 private:
     enum class ArithmeticOperation {
         Addition,
@@ -3734,6 +4000,34 @@
         }
     }
 
+    void branchForMoveConditionally(RelationalCondition condition, RegisterID lhs, RegisterID rhs, RISCV64Assembler::BImmediate offset)
+    {
+        switch (condition) {
+        case Equal:
+            return m_assembler.beqInsn(lhs, rhs, offset);
+        case NotEqual:
+            return m_assembler.bneInsn(lhs, rhs, offset);
+        case Above:
+            return m_assembler.bltuInsn(rhs, lhs, offset);
+        case AboveOrEqual:
+            return m_assembler.bgeuInsn(lhs, rhs, offset);
+        case Below:
+            return m_assembler.bltuInsn(lhs, rhs, offset);
+        case BelowOrEqual:
+            return m_assembler.bgeuInsn(rhs, lhs, offset);
+        case GreaterThan:
+            return m_assembler.bltInsn(rhs, lhs, offset);
+        case GreaterThanOrEqual:
+            return m_assembler.bgeInsn(lhs, rhs, offset);
+        case LessThan:
+            return m_assembler.bltInsn(lhs, rhs, offset);
+        case LessThanOrEqual:
+            return m_assembler.bgeInsn(rhs, lhs, offset);
+        }
+
+        RELEASE_ASSERT_NOT_REACHED();
+    }
+
     void compareFinalize(RelationalCondition cond, RegisterID lhs, RegisterID rhs, RegisterID dest)
     {
         switch (cond) {

Modified: trunk/Source/_javascript_Core/assembler/testmasm.cpp (293758 => 293759)


--- trunk/Source/_javascript_Core/assembler/testmasm.cpp	2022-05-04 03:17:09 UTC (rev 293758)
+++ trunk/Source/_javascript_Core/assembler/testmasm.cpp	2022-05-04 06:14:20 UTC (rev 293759)
@@ -3011,7 +3011,7 @@
 }
 #endif // CPU(X86) || CPU(X86_64) || CPU(ARM64)
 
-#if CPU(X86_64) || CPU(ARM64)
+#if CPU(X86_64) || CPU(ARM64) || CPU(RISCV64)
 
 template<typename T, typename SelectionType>
 void testMoveConditionallyFloatingPoint(MacroAssembler::DoubleCondition condition, const MacroAssemblerCodeRef<JSEntryPtrTag>& testCode, T& arg1, T& arg2, const Vector<T> operands, SelectionType selectionA, SelectionType selectionB)
@@ -3772,7 +3772,7 @@
     testMoveConditionallyFloatingPointSameArg(condition, testCode, arg1, floatOperands(), selectionA, selectionB);
 }
 
-#endif // CPU(X86_64) || CPU(ARM64)
+#endif // CPU(X86_64) || CPU(ARM64) || CPU(RISCV64)
 
 #if CPU(ARM64E)
 
@@ -4754,7 +4754,7 @@
     CPUState originalState;
     void* originalSP { nullptr };
     void* modifiedSP { nullptr };
-#if !(CPU(MIPS))
+#if !(CPU(MIPS) || CPU(RISCV64))
     uintptr_t modifiedFlags { 0 };
 #endif
     
@@ -4935,7 +4935,7 @@
     CPUState originalState;
     void* originalSP { nullptr };
     void* newSP { nullptr };
-#if !CPU(MIPS)
+#if !(CPU(MIPS) || CPU(RISCV64))
     uintptr_t modifiedFlags { 0 };
 #endif
     size_t numberOfExtraEntriesToWrite { 10 }; // ARM64 requires that this be 2 word aligned.
@@ -5903,7 +5903,7 @@
     FOR_EACH_DOUBLE_CONDITION_RUN(testCompareFloat);
 #endif
 
-#if CPU(X86_64) || CPU(ARM64)
+#if CPU(X86_64) || CPU(ARM64) || CPU(RISCV64)
     // Comparing 2 different registers.
     FOR_EACH_DOUBLE_CONDITION_RUN(testMoveConditionallyDouble2);
     FOR_EACH_DOUBLE_CONDITION_RUN(testMoveConditionallyDouble3);

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