Branch: refs/heads/main
Home: https://github.com/WebKit/WebKit
Commit: 08944322951dfdb47c7a53273eb55cba2482d000
https://github.com/WebKit/WebKit/commit/08944322951dfdb47c7a53273eb55cba2482d000
Author: David Degazio <[email protected]>
Date: 2022-12-22 (Thu, 22 Dec 2022)
Changed paths:
M Source/JavaScriptCore/b3/B3LowerMacros.cpp
M Source/JavaScriptCore/b3/B3LowerToAir.cpp
M Source/JavaScriptCore/b3/air/AirLowerMacros.cpp
M Source/JavaScriptCore/wasm/WasmAirIRGenerator64.cpp
M Source/JavaScriptCore/wasm/WasmB3IRGenerator.cpp
M Tools/Scripts/run-jsc-stress-tests
Log Message:
-----------
[WebAssembly SIMD] Get WasmB3IRGenerator to parity on Intel
https://bugs.webkit.org/show_bug.cgi?id=249745
rdar://103613145
Reviewed by Yusuke Suzuki.
Adds complete support for WebAssembly SIMD instructions to WasmB3IRGenerator.
With this,
every WebAssembly SIMD instruction is supported on Intel in every JSC compiler
tier. Because
of this, this patch also enables SIMD stress tests on x86_64 by default.
* Source/JavaScriptCore/b3/B3LowerToAir.cpp:
* Source/JavaScriptCore/wasm/WasmAirIRGenerator64.cpp:
(JSC::Wasm::AirIRGenerator64::addSIMDI_V):
(JSC::Wasm::AirIRGenerator64::addSIMDRelOp):
* Source/JavaScriptCore/wasm/WasmB3IRGenerator.cpp:
(JSC::Wasm::B3IRGenerator::addSIMDV_V):
(JSC::Wasm::B3IRGenerator::addSIMDRelOp):
(JSC::Wasm::B3IRGenerator::addSIMDSwizzleHelperX86):
(JSC::Wasm::B3IRGenerator::addSIMDV_VV):
(JSC::Wasm::B3IRGenerator::addSIMDExtmul):
(JSC::Wasm::B3IRGenerator::addSIMDShuffle):
* Tools/Scripts/run-jsc-stress-tests:
Canonical link: https://commits.webkit.org/258286@main
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