Branch: refs/heads/main
Home: https://github.com/WebKit/WebKit
Commit: 9affbf98e0099fe8f126bd9edba69f559d7fc33f
https://github.com/WebKit/WebKit/commit/9affbf98e0099fe8f126bd9edba69f559d7fc33f
Author: Wilmer Paulino <[email protected]>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
A JSTests/wasm/stress/simd-const-relaxed-lane-select.js
M Source/JavaScriptCore/b3/B3LowerToAir.cpp
M Source/JavaScriptCore/b3/B3LowerToAir32_64.cpp
M Source/JavaScriptCore/b3/B3Opcode.cpp
M Source/JavaScriptCore/b3/B3Opcode.h
M Source/JavaScriptCore/b3/B3SIMDValue.h
M Source/JavaScriptCore/b3/B3Validate.cpp
M Source/JavaScriptCore/b3/B3Value.cpp
M Source/JavaScriptCore/b3/B3Value.h
M Source/JavaScriptCore/b3/B3ValueInlines.h
M Source/JavaScriptCore/wasm/WasmFunctionParser.h
M Source/JavaScriptCore/wasm/WasmSIMDOpcodes.h
Log Message:
-----------
Implement relaxed laneselect SIMD instructions
https://bugs.webkit.org/show_bug.cgi?id=281581
Reviewed by Yusuke Suzuki.
The specification[1] notes that these instructions should behave as a
bitwise select SIMD instruction when the mask has either _all_ its bits
set or unset. When the mask is of any other value, it allows for
implementations to choose the behavior of the relaxed instruction based
on the backing architecture to be executed on.
The relaxed laneselect instructions are implemented for ARM64 as the
bitwise select (bsl) SIMD instruction since they are already natively
supported by the architecture.
For x86_64, CPUs without AVX support do not have an equivalent bsl
instruction. CPUs with SSE4.1 support feature an alternative set of
instructions (pblend) in which only the top bit of each lane within the
mask is examined. JSC requires AVX support for SIMD instructions, so
this is not applicable.
CPUs with AVX support have a similar instruction to ARM64's bsl, known
as vpblend. Note that this instruction is not currently used, and it is
instead emulated as v128.or(v128.and(v1, c), v128.and(v2, v128.not(c))).
This optimization can be deferred to future work. Nonetheless, we also
implement the relaxed laneselect instructions as a bitwise select for
x86_64 CPUs with AVX support.
[1]
https://github.com/WebAssembly/relaxed-simd/blob/main/proposals/relaxed-simd/Overview.md#relaxed-laneselect
* JSTests/wasm/stress/simd-const-relaxed-lane-select.js: Added.
(from.string_appeared_here.import.as.assert.from.string_appeared_here.let.wat.module.func.export.string_appeared_here.result.i32.i8x16.relaxed_laneselect.v128.const.i8x16.0.127.0.0.0.0.0.0.0.0.0.0.0.0.0.0.v128.const.i8x16.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.v128.const.i8x16.0.7.0.0.0.0.0.0.0.0.0.0.0.0.0.0.return.i8x16.extract_lane_u.1.func.export.string_appeared_here.result.i32.i16x8.relaxed_laneselect.v128.const.i16x8.0.32767.0.0.0.0.0.0.v128.const.i16x8.0.0.0.0.0.0.0.0.v128.const.i16x8.0.7.0.0.0.0.0.0.return.i16x8.extract_lane_u.1.func.export.string_appeared_here.result.i32.i32x4.relaxed_laneselect.v128.const.i32x4.0.2147483647.0.0.v128.const.i32x4.0.0.0.0.v128.const.i32x4.0.7.0.0.return.i32x4.extract_lane.1.func.export.string_appeared_here.result.i64.i64x2.relaxed_laneselect.v128.const.i64x2.0.9223372036854775807.v128.const.i64x2.0.0.v128.const.i64x2.0.7.return.i64x2.extract_lane.1.async
test):
* Source/JavaScriptCore/b3/B3LowerToAir.cpp:
* Source/JavaScriptCore/b3/B3LowerToAir32_64.cpp:
* Source/JavaScriptCore/b3/B3Opcode.cpp:
(WTF::printInternal):
* Source/JavaScriptCore/b3/B3Opcode.h:
* Source/JavaScriptCore/b3/B3SIMDValue.h:
* Source/JavaScriptCore/b3/B3Validate.cpp:
* Source/JavaScriptCore/b3/B3Value.cpp:
(JSC::B3::Value::effects const):
(JSC::B3::Value::key const):
* Source/JavaScriptCore/b3/B3Value.h:
* Source/JavaScriptCore/b3/B3ValueInlines.h:
* Source/JavaScriptCore/wasm/WasmBBQJIT64.cpp:
(JSC::Wasm::BBQJITImpl::BBQJIT::addSIMDBitwiseSelect):
* Source/JavaScriptCore/wasm/WasmFunctionParser.h:
(JSC::Wasm::FunctionParser<Context>::simd):
* Source/JavaScriptCore/wasm/WasmSIMDOpcodes.h:
(JSC::dumpSIMDLaneOperation):
(JSC::isRelaxedSIMDOperation):
Canonical link: https://commits.webkit.org/286162@main
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