[webkit-changes] [149676] trunk/Source/JavaScriptCore

Tue, 07 May 2013 09:51:40 -0700

Title: [149676] trunk/Source/_javascript_Core
Revision
149676
Author
[email protected]
Date
2013-05-07 09:53:23 -0700 (Tue, 07 May 2013)

Log Message

Take advantage of pre-decrement and post-increment opcodes for sh4 base JIT.
https://bugs.webkit.org/show_bug.cgi?id=115722

Patch by Julien Brianceau <[email protected]> on 2013-05-07
Reviewed by Oliver Hunt.

* assembler/MacroAssemblerSH4.h:
(JSC::MacroAssemblerSH4::load8PostInc):
(MacroAssemblerSH4):
(JSC::MacroAssemblerSH4::load16Unaligned):
(JSC::MacroAssemblerSH4::load16PostInc):
(JSC::MacroAssemblerSH4::storeDouble):
(JSC::MacroAssemblerSH4::load32WithUnalignedHalfWords):
* assembler/SH4Assembler.h:
(JSC::SH4Assembler::movwMemRegIn):
(SH4Assembler):
(JSC::SH4Assembler::movbMemRegIn):
(JSC::SH4Assembler::printInstr):

Modified Paths

Diff

Modified: trunk/Source/_javascript_Core/ChangeLog (149675 => 149676)


--- trunk/Source/_javascript_Core/ChangeLog	2013-05-07 16:24:19 UTC (rev 149675)
+++ trunk/Source/_javascript_Core/ChangeLog	2013-05-07 16:53:23 UTC (rev 149676)
@@ -1,3 +1,23 @@
+2013-05-07  Julien Brianceau  <[email protected]>
+
+        Take advantage of pre-decrement and post-increment opcodes for sh4 base JIT.
+        https://bugs.webkit.org/show_bug.cgi?id=115722
+
+        Reviewed by Oliver Hunt.
+
+        * assembler/MacroAssemblerSH4.h:
+        (JSC::MacroAssemblerSH4::load8PostInc):
+        (MacroAssemblerSH4):
+        (JSC::MacroAssemblerSH4::load16Unaligned):
+        (JSC::MacroAssemblerSH4::load16PostInc):
+        (JSC::MacroAssemblerSH4::storeDouble):
+        (JSC::MacroAssemblerSH4::load32WithUnalignedHalfWords):
+        * assembler/SH4Assembler.h:
+        (JSC::SH4Assembler::movwMemRegIn):
+        (SH4Assembler):
+        (JSC::SH4Assembler::movbMemRegIn):
+        (JSC::SH4Assembler::printInstr):
+
 2013-05-07  Anders Carlsson  <[email protected]>
 
         Remove AlwaysInline.h from WTF

Modified: trunk/Source/_javascript_Core/assembler/MacroAssemblerSH4.h (149675 => 149676)


--- trunk/Source/_javascript_Core/assembler/MacroAssemblerSH4.h	2013-05-07 16:24:19 UTC (rev 149675)
+++ trunk/Source/_javascript_Core/assembler/MacroAssemblerSH4.h	2013-05-07 16:53:23 UTC (rev 149676)
@@ -606,6 +606,12 @@
         releaseScratch(scr);
     }
 
+    void load8PostInc(RegisterID base, RegisterID dest)
+    {
+        m_assembler.movbMemRegIn(base, dest);
+        m_assembler.extub(dest, dest);
+    }
+
     void load8Signed(BaseIndex address, RegisterID dest)
     {
         RegisterID scr = claimScratch();
@@ -736,8 +742,7 @@
             add32(TrustedImm32(address.offset), scr);
 
         add32(address.base, scr);
-        load8(scr, scr1);
-        add32(TrustedImm32(1), scr);
+        load8PostInc(scr, scr1);
         load8(scr, dest);
         m_assembler.shllImm8r(8, dest);
         or32(scr1, dest);
@@ -763,6 +768,12 @@
         m_assembler.extuw(dest, dest);
     }
 
+    void load16PostInc(RegisterID base, RegisterID dest)
+    {
+        m_assembler.movwMemRegIn(base, dest);
+        m_assembler.extuw(dest, dest);
+    }
+
     void load16Signed(BaseIndex address, RegisterID dest)
     {
         RegisterID scr = claimScratch();
@@ -1029,11 +1040,10 @@
     void storeDouble(FPRegisterID src, ImplicitAddress address)
     {
         RegisterID scr = claimScratch();
-        m_assembler.loadConstant(address.offset, scr);
+        m_assembler.loadConstant(address.offset + 8, scr);
         m_assembler.addlRegReg(address.base, scr);
-        m_assembler.fmovsWriterm((FPRegisterID)(src + 1), scr);
-        m_assembler.addlImm8r(4, scr);
-        m_assembler.fmovsWriterm(src, scr);
+        m_assembler.fmovsWriterndec(src, scr);
+        m_assembler.fmovsWriterndec((FPRegisterID)(src + 1), scr);
         releaseScratch(scr);
     }
 
@@ -1044,12 +1054,10 @@
         move(address.index, scr);
         lshift32(TrustedImm32(address.scale), scr);
         add32(address.base, scr);
-        if (address.offset)
-            add32(TrustedImm32(address.offset), scr);
+        add32(TrustedImm32(address.offset + 8), scr);
 
-        m_assembler.fmovsWriterm((FPRegisterID)(src + 1), scr);
-        m_assembler.addlImm8r(4, scr);
-        m_assembler.fmovsWriterm(src, scr);
+        m_assembler.fmovsWriterndec(src, scr);
+        m_assembler.fmovsWriterndec((FPRegisterID)(src + 1), scr);
 
         releaseScratch(scr);
     }
@@ -1159,11 +1167,11 @@
         if (address.offset)
             add32(TrustedImm32(address.offset), scr);
 
-        m_assembler.ensureSpace(m_assembler.maxInstructionSize + 68, sizeof(uint32_t));
+        m_assembler.ensureSpace(m_assembler.maxInstructionSize + 58, sizeof(uint32_t));
         move(scr, SH4Registers::r0);
-        m_assembler.andlImm8r(0x3, SH4Registers::r0);
-        m_assembler.cmpEqImmR0(0x0, SH4Registers::r0);
+        m_assembler.testlImm8r(0x3, SH4Registers::r0);
         m_jump = Jump(m_assembler.jne(), SH4Assembler::JumpNear);
+
         if (dest != SH4Registers::r0)
             move(scr1, SH4Registers::r0);
 
@@ -1171,27 +1179,23 @@
         end.append(Jump(m_assembler.bra(), SH4Assembler::JumpNear));
         m_assembler.nop();
         m_jump.link(this);
-        m_assembler.andlImm8r(0x1, SH4Registers::r0);
-        m_assembler.cmpEqImmR0(0x0, SH4Registers::r0);
+        m_assembler.testlImm8r(0x1, SH4Registers::r0);
 
         if (dest != SH4Registers::r0)
             move(scr1, SH4Registers::r0);
 
         m_jump = Jump(m_assembler.jne(), SH4Assembler::JumpNear);
-        load16(scr, scr1);
-        add32(TrustedImm32(2), scr);
+        load16PostInc(scr, scr1);
         load16(scr, dest);
         m_assembler.shllImm8r(16, dest);
         or32(scr1, dest);
         end.append(Jump(m_assembler.bra(), SH4Assembler::JumpNear));
         m_assembler.nop();
         m_jump.link(this);
-        load8(scr, scr1);
-        add32(TrustedImm32(1), scr);
-        load16(scr, dest);
+        load8PostInc(scr, scr1);
+        load16PostInc(scr, dest);
         m_assembler.shllImm8r(8, dest);
         or32(dest, scr1);
-        add32(TrustedImm32(2), scr);
         load8(scr, dest);
         m_assembler.shllImm8r(8, dest);
         m_assembler.shllImm8r(16, dest);

Modified: trunk/Source/_javascript_Core/assembler/SH4Assembler.h (149675 => 149676)


--- trunk/Source/_javascript_Core/assembler/SH4Assembler.h	2013-05-07 16:24:19 UTC (rev 149675)
+++ trunk/Source/_javascript_Core/assembler/SH4Assembler.h	2013-05-07 16:53:23 UTC (rev 149676)
@@ -117,6 +117,7 @@
     MOVW_WRITE_RN_OPCODE = 0x2001,
     MOVW_WRITE_R0RN_OPCODE = 0x0005,
     MOVW_READ_RM_OPCODE = 0x6001,
+    MOVW_READ_RMINC_OPCODE = 0x6005,
     MOVW_READ_R0RM_OPCODE = 0x000d,
     MOVW_READ_OFFRM_OPCODE = 0x8500,
     MOVW_READ_OFFPC_OPCODE = 0x9000,
@@ -1038,6 +1039,12 @@
         oneShortOp(opc);
     }
 
+    void movwMemRegIn(RegisterID base, RegisterID dst)
+    {
+        uint16_t opc = getOpcodeGroup1(MOVW_READ_RMINC_OPCODE, dst, base);
+        oneShortOp(opc);
+    }
+
     void movwPCReg(int offset, RegisterID base, RegisterID dst)
     {
         ASSERT(base == SH4Registers::pc);
@@ -1133,6 +1140,12 @@
         oneShortOp(opc);
     }
 
+    void movbMemRegIn(RegisterID base, RegisterID dst)
+    {
+        uint16_t opc = getOpcodeGroup1(MOVB_READ_RMINC_OPCODE, dst, base);
+        oneShortOp(opc);
+    }
+
     void movbRegMemr0(RegisterID src, RegisterID dst)
     {
         uint16_t opc = getOpcodeGroup1(MOVB_WRITE_R0RN_OPCODE, dst, src);
@@ -1958,6 +1971,9 @@
         case MOVW_READ_RM_OPCODE:
             format = "    MOV.W @R%d, R%d\n";
             break;
+        case MOVW_READ_RMINC_OPCODE:
+            format = "    MOV.W @R%d+, R%d\n";
+            break;
         case MOVW_READ_R0RM_OPCODE:
             format = "    MOV.W @(R0, R%d), R%d\n";
             break;

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