[webkit-changes] [172746] trunk/Source/JavaScriptCore

Tue, 19 Aug 2014 00:15:07 -0700

Title: [172746] trunk/Source/_javascript_Core
Revision
172746
Author
[email protected]
Date
2014-08-19 00:14:30 -0700 (Tue, 19 Aug 2014)

Log Message

REGRESSION(r163179): It broke the build on ARM Thumb2 with GCC
https://bugs.webkit.org/show_bug.cgi?id=136028

Patch by Michael Saboff <[email protected]> on 2014-08-19
Reviewed by Oliver Hunt.

Added back ARMv7 conditionals around three op addp and subp since ARM Thumb2 spec says that
the behavior for those ops are undefined.  This was originally done in changeset 163179.

* llint/LowLevelInterpreter32_64.asm:

Modified Paths

Diff

Modified: trunk/Source/_javascript_Core/ChangeLog (172745 => 172746)


--- trunk/Source/_javascript_Core/ChangeLog	2014-08-19 06:12:49 UTC (rev 172745)
+++ trunk/Source/_javascript_Core/ChangeLog	2014-08-19 07:14:30 UTC (rev 172746)
@@ -1,3 +1,15 @@
+2014-08-19  Michael Saboff  <[email protected]>
+
+        REGRESSION(r163179): It broke the build on ARM Thumb2 with GCC
+        https://bugs.webkit.org/show_bug.cgi?id=136028
+
+        Reviewed by Oliver Hunt.
+
+        Added back ARMv7 conditionals around three op addp and subp since ARM Thumb2 spec says that
+        the behavior for those ops are undefined.  This was originally done in changeset 163179.
+
+        * llint/LowLevelInterpreter32_64.asm:
+
 2014-08-18  Commit Queue  <[email protected]>
 
         Unreviewed, rolling out r172741.

Modified: trunk/Source/_javascript_Core/llint/LowLevelInterpreter32_64.asm (172745 => 172746)


--- trunk/Source/_javascript_Core/llint/LowLevelInterpreter32_64.asm	2014-08-19 06:12:49 UTC (rev 172745)
+++ trunk/Source/_javascript_Core/llint/LowLevelInterpreter32_64.asm	2014-08-19 07:14:30 UTC (rev 172746)
@@ -203,7 +203,12 @@
         loadp 8[cfr], entry
     end
 
-    vmEntryRecord(cfr, sp)
+    if ARMv7
+        vmEntryRecord(cfr, temp1)
+        move temp1, sp
+    else
+        vmEntryRecord(cfr, sp)
+    end
 
     storep vm, VMEntryRecord::m_vm[sp]
     loadp VM::topCallFrame[vm], temp2
@@ -219,7 +224,12 @@
     elsif ARM or ARMv7 or ARMv7_TRADITIONAL
         addp CallFrameAlignSlots * SlotSize, sp, temp1
         clrbp temp1, StackAlignmentMask, temp1
-        subp temp1, CallFrameAlignSlots * SlotSize, sp
+        if ARMv7
+            subp temp1, CallFrameAlignSlots * SlotSize, temp1
+            move temp1, sp
+        else
+            subp temp1, CallFrameAlignSlots * SlotSize, sp
+        end
     end
 
     if X86 or X86_WIN
@@ -252,7 +262,12 @@
 
     cCall2(_llint_throw_stack_overflow_error, vm, protoCallFrame)
 
-    vmEntryRecord(cfr, sp)
+    if ARMv7
+        vmEntryRecord(cfr, temp1)
+        move temp1, sp
+    else
+        vmEntryRecord(cfr, sp)
+    end
 
     loadp VMEntryRecord::m_vm[sp], temp3
     loadp VMEntryRecord::m_prevTopCallFrame[sp], temp4
@@ -260,7 +275,12 @@
     loadp VMEntryRecord::m_prevTopVMEntryFrame[sp], temp4
     storep temp4, VM::topVMEntryFrame[temp3]
 
-    subp cfr, CalleeRegisterSaveSize, sp
+    if ARMv7
+        subp cfr, CalleeRegisterSaveSize, temp3
+        move temp3, sp
+    else
+        subp cfr, CalleeRegisterSaveSize, sp
+    end
 
     popCalleeSaves()
     functionEpilogue()
@@ -308,7 +328,12 @@
 
     makeCall(entry, temp1, temp2)
 
-    vmEntryRecord(cfr, sp)
+    if ARMv7
+        vmEntryRecord(cfr, temp1)
+        move temp1, sp
+    else
+        vmEntryRecord(cfr, sp)
+    end
 
     loadp VMEntryRecord::m_vm[sp], temp3
     loadp VMEntryRecord::m_prevTopCallFrame[sp], temp4
@@ -316,7 +341,12 @@
     loadp VMEntryRecord::m_prevTopVMEntryFrame[sp], temp4
     storep temp4, VM::topVMEntryFrame[temp3]
 
-    subp cfr, CalleeRegisterSaveSize, sp
+    if ARMv7
+        subp cfr, CalleeRegisterSaveSize, temp3
+        move temp3, sp
+    else
+        subp cfr, CalleeRegisterSaveSize, sp
+    end
 
     popCalleeSaves()
     functionEpilogue()
@@ -372,7 +402,12 @@
 
     loadp CallerFrame + PayloadOffset[cfr], cfr
 
-    vmEntryRecord(cfr, sp)
+    if ARMv7
+        vmEntryRecord(cfr, t3)
+        move t3, sp
+    else
+        vmEntryRecord(cfr, sp)
+    end
 
     loadp VMEntryRecord::m_vm[sp], t3
     loadp VMEntryRecord::m_prevTopCallFrame[sp], t5
@@ -380,7 +415,12 @@
     loadp VMEntryRecord::m_prevTopVMEntryFrame[sp], t5
     storep t5, VM::topVMEntryFrame[t3]
 
-    subp cfr, CalleeRegisterSaveSize, sp
+    if ARMv7
+        subp cfr, CalleeRegisterSaveSize, t3
+        move t3, sp
+    else
+        subp cfr, CalleeRegisterSaveSize, sp
+    end
 
     popCalleeSaves()
     functionEpilogue()

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