Diff
Modified: trunk/Source/_javascript_Core/ChangeLog (194387 => 194388)
--- trunk/Source/_javascript_Core/ChangeLog 2015-12-23 10:48:26 UTC (rev 194387)
+++ trunk/Source/_javascript_Core/ChangeLog 2015-12-23 11:52:39 UTC (rev 194388)
@@ -1,3 +1,69 @@
+2015-12-23 Benjamin Poulain <[email protected]>
+
+ [JSC] Get the _javascript_Core framework to build on ARM64 with B3 enabled
+ https://bugs.webkit.org/show_bug.cgi?id=152503
+
+ Reviewed by Filip Pizlo.
+
+ It is not working but it builds.
+
+ * assembler/ARM64Assembler.h:
+ (JSC::ARM64Assembler::vand):
+ (JSC::ARM64Assembler::vectorDataProcessing2Source):
+ * assembler/MacroAssemblerARM64.h:
+ (JSC::MacroAssemblerARM64::add32):
+ (JSC::MacroAssemblerARM64::add64):
+ (JSC::MacroAssemblerARM64::countLeadingZeros64):
+ (JSC::MacroAssemblerARM64::not32):
+ (JSC::MacroAssemblerARM64::not64):
+ (JSC::MacroAssemblerARM64::zeroExtend16To32):
+ (JSC::MacroAssemblerARM64::signExtend16To32):
+ (JSC::MacroAssemblerARM64::zeroExtend8To32):
+ (JSC::MacroAssemblerARM64::signExtend8To32):
+ (JSC::MacroAssemblerARM64::addFloat):
+ (JSC::MacroAssemblerARM64::ceilFloat):
+ (JSC::MacroAssemblerARM64::branchDouble):
+ (JSC::MacroAssemblerARM64::branchFloat):
+ (JSC::MacroAssemblerARM64::divFloat):
+ (JSC::MacroAssemblerARM64::moveZeroToDouble):
+ (JSC::MacroAssemblerARM64::moveFloatTo32):
+ (JSC::MacroAssemblerARM64::move32ToFloat):
+ (JSC::MacroAssemblerARM64::moveConditionallyDouble):
+ (JSC::MacroAssemblerARM64::moveConditionallyFloat):
+ (JSC::MacroAssemblerARM64::moveConditionallyAfterFloatingPointCompare):
+ (JSC::MacroAssemblerARM64::mulFloat):
+ (JSC::MacroAssemblerARM64::andDouble):
+ (JSC::MacroAssemblerARM64::andFloat):
+ (JSC::MacroAssemblerARM64::sqrtFloat):
+ (JSC::MacroAssemblerARM64::subFloat):
+ (JSC::MacroAssemblerARM64::signExtend32ToPtr):
+ (JSC::MacroAssemblerARM64::moveConditionally32):
+ (JSC::MacroAssemblerARM64::moveConditionally64):
+ (JSC::MacroAssemblerARM64::moveConditionallyTest32):
+ (JSC::MacroAssemblerARM64::moveConditionallyTest64):
+ (JSC::MacroAssemblerARM64::test32):
+ (JSC::MacroAssemblerARM64::setCarry):
+ (JSC::MacroAssemblerARM64::jumpAfterFloatingPointCompare):
+ * assembler/MacroAssemblerX86.h:
+ (JSC::MacroAssemblerX86::moveDoubleToInts):
+ (JSC::MacroAssemblerX86::moveIntsToDouble):
+ * assembler/MacroAssemblerX86Common.h:
+ (JSC::MacroAssemblerX86Common::move32ToFloat):
+ (JSC::MacroAssemblerX86Common::moveFloatTo32):
+ (JSC::MacroAssemblerX86Common::moveInt32ToPacked): Deleted.
+ (JSC::MacroAssemblerX86Common::movePackedToInt32): Deleted.
+ * b3/B3LowerToAir.cpp:
+ (JSC::B3::Air::LowerToAir::appendShift):
+ (JSC::B3::Air::LowerToAir::lower):
+ * b3/air/AirInstInlines.h:
+ (JSC::B3::Air::isX86DivHelperValid):
+ * b3/air/AirOpcode.opcodes:
+ * jit/AssemblyHelpers.h:
+ (JSC::AssemblyHelpers::emitFunctionEpilogueWithEmptyFrame):
+ (JSC::AssemblyHelpers::emitFunctionEpilogue):
+ * jit/FPRInfo.h:
+ (JSC::FPRInfo::toArgumentRegister):
+
2015-12-23 Andy VanWagoner <[email protected]>
[INTL] Implement Intl.DateTimeFormat.prototype.resolvedOptions ()
Modified: trunk/Source/_javascript_Core/assembler/ARM64Assembler.h (194387 => 194388)
--- trunk/Source/_javascript_Core/assembler/ARM64Assembler.h 2015-12-23 10:48:26 UTC (rev 194387)
+++ trunk/Source/_javascript_Core/assembler/ARM64Assembler.h 2015-12-23 11:52:39 UTC (rev 194388)
@@ -38,6 +38,7 @@
#define DATASIZE_OF(datasize) ((datasize == 64) ? Datasize_64 : Datasize_32)
#define MEMOPSIZE_OF(datasize) ((datasize == 8 || datasize == 128) ? MemOpSize_8_or_128 : (datasize == 16) ? MemOpSize_16 : (datasize == 32) ? MemOpSize_32 : MemOpSize_64)
#define CHECK_DATASIZE() CHECK_DATASIZE_OF(datasize)
+#define CHECK_VECTOR_DATASIZE() ASSERT(datasize == 64 || datasize == 128)
#define DATASIZE DATASIZE_OF(datasize)
#define MEMOPSIZE MEMOPSIZE_OF(datasize)
#define CHECK_FP_MEMOP_DATASIZE() ASSERT(datasize == 8 || datasize == 16 || datasize == 32 || datasize == 64 || datasize == 128)
@@ -861,6 +862,10 @@
FPDataOp_FNMUL
};
+ enum SIMD3Same {
+ SIMD_LogicalOp_AND = 0x03
+ };
+
enum FPIntConvOp {
FPIntConvOp_FCVTNS = 0x00,
FPIntConvOp_FCVTNU = 0x01,
@@ -2418,6 +2423,13 @@
}
template<int datasize>
+ ALWAYS_INLINE void vand(FPRegisterID vd, FPRegisterID vn, FPRegisterID vm)
+ {
+ CHECK_VECTOR_DATASIZE();
+ insn(vectorDataProcessing2Source(SIMD_LogicalOp_AND, vm, vn, vd));
+ }
+
+ template<int datasize>
ALWAYS_INLINE void frinta(FPRegisterID vd, FPRegisterID vn)
{
CHECK_DATASIZE();
@@ -3473,6 +3485,18 @@
return (0x1e200800 | M << 31 | S << 29 | type << 22 | rm << 16 | opcode << 12 | rn << 5 | rd);
}
+ ALWAYS_INLINE static int vectorDataProcessing2Source(SIMD3Same opcode, unsigned size, FPRegisterID vm, FPRegisterID vn, FPRegisterID vd)
+ {
+ const int Q = 0;
+ return (0xe201c00 | Q << 30 | size << 22 | vm << 16 | opcode << 11 | vn << 5 | vd);
+ }
+
+ ALWAYS_INLINE static int vectorDataProcessing2Source(SIMD3Same opcode, FPRegisterID vm, FPRegisterID vn, FPRegisterID vd)
+ {
+ return vectorDataProcessing2Source(opcode, 0, vm, vn, vd);
+ }
+
+
// 'o1' means negate
ALWAYS_INLINE static int floatingPointDataProcessing3Source(Datasize type, bool o1, FPRegisterID rm, AddOp o2, FPRegisterID ra, FPRegisterID rn, FPRegisterID rd)
{
Modified: trunk/Source/_javascript_Core/assembler/MacroAssemblerARM64.h (194387 => 194388)
--- trunk/Source/_javascript_Core/assembler/MacroAssemblerARM64.h 2015-12-23 10:48:26 UTC (rev 194387)
+++ trunk/Source/_javascript_Core/assembler/MacroAssemblerARM64.h 2015-12-23 11:52:39 UTC (rev 194388)
@@ -134,6 +134,12 @@
// Integer operations:
+ void add32(RegisterID a, RegisterID b, RegisterID dest)
+ {
+ ASSERT(a != ARM64Registers::sp && b != ARM64Registers::sp);
+ m_assembler.add<32>(dest, a, b);
+ }
+
void add32(RegisterID src, RegisterID dest)
{
m_assembler.add<32>(dest, dest, src);
@@ -213,6 +219,14 @@
add32(dataTempRegister, dest);
}
+ void add64(RegisterID a, RegisterID b, RegisterID dest)
+ {
+ ASSERT(a != ARM64Registers::sp || b != ARM64Registers::sp);
+ if (b == ARM64Registers::sp)
+ std::swap(a, b);
+ m_assembler.add<64>(dest, a, b);
+ }
+
void add64(RegisterID src, RegisterID dest)
{
if (src == ARM64Registers::sp)
@@ -408,6 +422,11 @@
m_assembler.clz<32>(dest, src);
}
+ void countLeadingZeros64(RegisterID src, RegisterID dest)
+ {
+ m_assembler.clz<64>(dest, src);
+ }
+
void lshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
{
m_assembler.lsl<32>(dest, src, shiftAmount);
@@ -813,7 +832,16 @@
}
}
+ void not32(RegisterID src, RegisterID dest)
+ {
+ m_assembler.mvn<32>(dest, src);
+ }
+ void not64(RegisterID src, RegisterID dest)
+ {
+ m_assembler.mvn<64>(dest, src);
+ }
+
// Memory access operations:
void load64(ImplicitAddress address, RegisterID dest)
@@ -963,6 +991,16 @@
m_assembler.ldrsh<32>(dest, address.base, memoryTempRegister);
}
+ void zeroExtend16To32(RegisterID src, RegisterID dest)
+ {
+ m_assembler.uxth<64>(dest, src);
+ }
+
+ void signExtend16To32(RegisterID src, RegisterID dest)
+ {
+ m_assembler.sxth<64>(dest, src);
+ }
+
void load8(ImplicitAddress address, RegisterID dest)
{
if (tryLoadWithOffset<8>(dest, address.base, address.offset))
@@ -1004,6 +1042,16 @@
m_assembler.ldrsb<32>(dest, address.base, memoryTempRegister);
}
+ void zeroExtend8To32(RegisterID src, RegisterID dest)
+ {
+ m_assembler.uxtb<64>(dest, src);
+ }
+
+ void signExtend8To32(RegisterID src, RegisterID dest)
+ {
+ m_assembler.sxtb<64>(dest, src);
+ }
+
void store64(RegisterID src, ImplicitAddress address)
{
if (tryStoreWithOffset<64>(src, address.base, address.offset))
@@ -1230,11 +1278,21 @@
addDouble(fpTempRegister, dest);
}
+ void addFloat(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
+ {
+ m_assembler.fadd<32>(dest, op1, op2);
+ }
+
void ceilDouble(FPRegisterID src, FPRegisterID dest)
{
m_assembler.frintp<64>(dest, src);
}
+ void ceilFloat(FPRegisterID src, FPRegisterID dest)
+ {
+ m_assembler.frintp<32>(dest, src);
+ }
+
void floorDouble(FPRegisterID src, FPRegisterID dest)
{
m_assembler.frintm<64>(dest, src);
@@ -1265,24 +1323,13 @@
Jump branchDouble(DoubleCondition cond, FPRegisterID left, FPRegisterID right)
{
m_assembler.fcmp<64>(left, right);
+ return jumpAfterFloatingPointCompare(cond);
+ }
- if (cond == DoubleNotEqual) {
- // ConditionNE jumps if NotEqual *or* unordered - force the unordered cases not to jump.
- Jump unordered = makeBranch(ARM64Assembler::ConditionVS);
- Jump result = makeBranch(ARM64Assembler::ConditionNE);
- unordered.link(this);
- return result;
- }
- if (cond == DoubleEqualOrUnordered) {
- Jump unordered = makeBranch(ARM64Assembler::ConditionVS);
- Jump notEqual = makeBranch(ARM64Assembler::ConditionNE);
- unordered.link(this);
- // We get here if either unordered or equal.
- Jump result = jump();
- notEqual.link(this);
- return result;
- }
- return makeBranch(cond);
+ Jump branchFloat(DoubleCondition cond, FPRegisterID left, FPRegisterID right)
+ {
+ m_assembler.fcmp<32>(left, right);
+ return jumpAfterFloatingPointCompare(cond);
}
Jump branchDoubleNonZero(FPRegisterID reg, FPRegisterID)
@@ -1364,6 +1411,11 @@
m_assembler.fdiv<64>(dest, op1, op2);
}
+ void divFloat(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
+ {
+ m_assembler.fdiv<32>(dest, op1, op2);
+ }
+
void loadDouble(ImplicitAddress address, FPRegisterID dest)
{
if (tryLoadWithOffset<64>(dest, address.base, address.offset))
@@ -1408,16 +1460,64 @@
m_assembler.fmov<64>(dest, src);
}
+ void moveZeroToDouble(FPRegisterID reg)
+ {
+ m_assembler.fmov<64>(reg, ARM64Registers::zr);
+ }
+
void moveDoubleTo64(FPRegisterID src, RegisterID dest)
{
m_assembler.fmov<64>(dest, src);
}
+ void moveFloatTo32(FPRegisterID src, RegisterID dest)
+ {
+ m_assembler.fmov<32>(dest, src);
+ }
+
void move64ToDouble(RegisterID src, FPRegisterID dest)
{
m_assembler.fmov<64>(dest, src);
}
+ void move32ToFloat(RegisterID src, FPRegisterID dest)
+ {
+ m_assembler.fmov<32>(dest, src);
+ }
+
+ void moveConditionallyDouble(DoubleCondition cond, FPRegisterID left, FPRegisterID right, RegisterID src, RegisterID dest)
+ {
+ m_assembler.fcmp<64>(left, right);
+ moveConditionallyAfterFloatingPointCompare<64>(cond, src, dest);
+ }
+
+ void moveConditionallyFloat(DoubleCondition cond, FPRegisterID left, FPRegisterID right, RegisterID src, RegisterID dest)
+ {
+ m_assembler.fcmp<32>(left, right);
+ moveConditionallyAfterFloatingPointCompare<64>(cond, src, dest);
+ }
+
+ template<int datasize>
+ void moveConditionallyAfterFloatingPointCompare(DoubleCondition cond, RegisterID src, RegisterID dest)
+ {
+ if (cond == DoubleNotEqual) {
+ Jump unordered = makeBranch(ARM64Assembler::ConditionVS);
+ m_assembler.csel<datasize>(dest, src, dest, ARM64Assembler::ConditionNE);
+ unordered.link(this);
+ return;
+ }
+ if (cond == DoubleEqualOrUnordered) {
+ // If the compare is unordered, src is copied to dest and the
+ // next csel has all arguments equal to src.
+ // If the compare is ordered, dest is unchanged and EQ decides
+ // what value to set.
+ m_assembler.csel<datasize>(dest, src, dest, ARM64Assembler::ConditionVS);
+ m_assembler.csel<datasize>(dest, src, dest, ARM64Assembler::ConditionEQ);
+ return;
+ }
+ m_assembler.csel<datasize>(dest, src, dest, ARM64Condition(cond));
+ }
+
void mulDouble(FPRegisterID src, FPRegisterID dest)
{
mulDouble(dest, src, dest);
@@ -1434,6 +1534,21 @@
mulDouble(fpTempRegister, dest);
}
+ void mulFloat(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
+ {
+ m_assembler.fmul<32>(dest, op1, op2);
+ }
+
+ void andDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
+ {
+ m_assembler.vand<64>(dest, op1, op2);
+ }
+
+ void andFloat(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
+ {
+ andDouble(op1, op2, dest);
+ }
+
void negateDouble(FPRegisterID src, FPRegisterID dest)
{
m_assembler.fneg<64>(dest, src);
@@ -1444,6 +1559,11 @@
m_assembler.fsqrt<64>(dest, src);
}
+ void sqrtFloat(FPRegisterID src, FPRegisterID dest)
+ {
+ m_assembler.fsqrt<32>(dest, src);
+ }
+
void storeDouble(FPRegisterID src, ImplicitAddress address)
{
if (tryStoreWithOffset<64>(src, address.base, address.offset))
@@ -1499,6 +1619,11 @@
subDouble(fpTempRegister, dest);
}
+ void subFloat(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
+ {
+ m_assembler.fsub<32>(dest, op1, op2);
+ }
+
// Result is undefined if the value is outside of the integer range.
void truncateDoubleToInt32(FPRegisterID src, RegisterID dest)
{
@@ -1628,6 +1753,11 @@
move(reg2, reg1);
move(dataTempRegister, reg2);
}
+
+ void signExtend32ToPtr(TrustedImm32 imm, RegisterID dest)
+ {
+ move(TrustedImmPtr(reinterpret_cast<void*>(static_cast<intptr_t>(imm.m_value))), dest);
+ }
void signExtend32ToPtr(RegisterID src, RegisterID dest)
{
@@ -1639,7 +1769,30 @@
m_assembler.uxtw(dest, src);
}
+ void moveConditionally32(RelationalCondition cond, RegisterID left, RegisterID right, RegisterID src, RegisterID dest)
+ {
+ m_assembler.cmp<32>(left, right);
+ m_assembler.csel<32>(dest, src, dest, ARM64Condition(cond));
+ }
+ void moveConditionally64(RelationalCondition cond, RegisterID left, RegisterID right, RegisterID src, RegisterID dest)
+ {
+ m_assembler.cmp<64>(left, right);
+ m_assembler.csel<64>(dest, src, dest, ARM64Condition(cond));
+ }
+
+ void moveConditionallyTest32(ResultCondition cond, RegisterID testReg, RegisterID mask, RegisterID src, RegisterID dest)
+ {
+ m_assembler.tst<32>(testReg, mask);
+ m_assembler.csel<32>(dest, src, dest, ARM64Condition(cond));
+ }
+
+ void moveConditionallyTest64(ResultCondition cond, RegisterID testReg, RegisterID mask, RegisterID src, RegisterID dest)
+ {
+ m_assembler.tst<64>(testReg, mask);
+ m_assembler.csel<64>(dest, src, dest, ARM64Condition(cond));
+ }
+
// Forwards / external control flow operations:
//
// This set of jump and conditional branch operations return a Jump
@@ -2314,7 +2467,13 @@
move(right, getCachedDataTempRegisterIDAndInvalidate());
compare32(cond, memoryTempRegister, dataTempRegister, dest);
}
-
+
+ void test32(ResultCondition cond, RegisterID src, RegisterID mask, RegisterID dest)
+ {
+ m_assembler.tst<32>(src, mask);
+ m_assembler.cset<32>(dest, ARM64Condition(cond));
+ }
+
void test32(ResultCondition cond, RegisterID src, TrustedImm32 mask, RegisterID dest)
{
if (mask.m_value == -1)
@@ -2355,6 +2514,10 @@
m_assembler.cset<32>(dest, ARM64Condition(cond));
}
+ void setCarry(RegisterID dest)
+ {
+ m_assembler.cset<32>(dest, ARM64Assembler::ConditionCS);
+ }
// Patchable operations
@@ -2742,11 +2905,6 @@
}
}
- void signExtend32ToPtr(TrustedImm32 imm, RegisterID dest)
- {
- move(TrustedImmPtr(reinterpret_cast<void*>(static_cast<intptr_t>(imm.m_value))), dest);
- }
-
template<int datasize>
ALWAYS_INLINE void load(const void* address, RegisterID dest)
{
@@ -2933,6 +3091,27 @@
return false;
}
+ Jump jumpAfterFloatingPointCompare(DoubleCondition cond)
+ {
+ if (cond == DoubleNotEqual) {
+ // ConditionNE jumps if NotEqual *or* unordered - force the unordered cases not to jump.
+ Jump unordered = makeBranch(ARM64Assembler::ConditionVS);
+ Jump result = makeBranch(ARM64Assembler::ConditionNE);
+ unordered.link(this);
+ return result;
+ }
+ if (cond == DoubleEqualOrUnordered) {
+ Jump unordered = makeBranch(ARM64Assembler::ConditionVS);
+ Jump notEqual = makeBranch(ARM64Assembler::ConditionNE);
+ unordered.link(this);
+ // We get here if either unordered or equal.
+ Jump result = jump();
+ notEqual.link(this);
+ return result;
+ }
+ return makeBranch(cond);
+ }
+
friend class LinkBuffer;
static void linkCall(void* code, Call call, FunctionPtr function)
Modified: trunk/Source/_javascript_Core/assembler/MacroAssemblerX86.h (194387 => 194388)
--- trunk/Source/_javascript_Core/assembler/MacroAssemblerX86.h 2015-12-23 10:48:26 UTC (rev 194387)
+++ trunk/Source/_javascript_Core/assembler/MacroAssemblerX86.h 2015-12-23 11:52:39 UTC (rev 194388)
@@ -179,13 +179,13 @@
m_assembler.pextrw_irr(2, src, dest2);
lshift32(TrustedImm32(16), dest1);
or32(dest1, dest2);
- movePackedToInt32(src, dest1);
+ moveFloatTo32(src, dest1);
}
void moveIntsToDouble(RegisterID src1, RegisterID src2, FPRegisterID dest, FPRegisterID scratch)
{
- moveInt32ToPacked(src1, dest);
- moveInt32ToPacked(src2, scratch);
+ move32ToFloat(src1, dest);
+ move32ToFloat(src2, scratch);
lshiftPacked(TrustedImm32(32), scratch);
orPacked(scratch, dest);
}
Modified: trunk/Source/_javascript_Core/assembler/MacroAssemblerX86Common.h (194387 => 194388)
--- trunk/Source/_javascript_Core/assembler/MacroAssemblerX86Common.h 2015-12-23 10:48:26 UTC (rev 194387)
+++ trunk/Source/_javascript_Core/assembler/MacroAssemblerX86Common.h 2015-12-23 11:52:39 UTC (rev 194388)
@@ -1208,13 +1208,13 @@
m_assembler.por_rr(src, dst);
}
- void moveInt32ToPacked(RegisterID src, XMMRegisterID dst)
+ void move32ToFloat(RegisterID src, XMMRegisterID dst)
{
ASSERT(isSSE2Present());
m_assembler.movd_rr(src, dst);
}
- void movePackedToInt32(XMMRegisterID src, RegisterID dst)
+ void moveFloatTo32(XMMRegisterID src, RegisterID dst)
{
ASSERT(isSSE2Present());
m_assembler.movd_rr(src, dst);
Modified: trunk/Source/_javascript_Core/b3/B3LowerToAir.cpp (194387 => 194388)
--- trunk/Source/_javascript_Core/b3/B3LowerToAir.cpp 2015-12-23 10:48:26 UTC (rev 194387)
+++ trunk/Source/_javascript_Core/b3/B3LowerToAir.cpp 2015-12-23 11:52:39 UTC (rev 194388)
@@ -644,14 +644,27 @@
Air::Opcode opcode = opcodeForType(opcode32, opcode64, value->type());
if (imm(amount)) {
- append(Move, tmp(value), tmp(m_value));
- append(opcode, imm(amount), tmp(m_value));
+ if (isValidForm(opcode, Arg::Tmp, Arg::Imm, Arg::Tmp)) {
+ append(opcode, tmp(value), imm(amount), tmp(m_value));
+ return;
+ }
+ if (isValidForm(opcode, Arg::Imm, Arg::Tmp)) {
+ append(Move, tmp(value), tmp(m_value));
+ append(opcode, imm(amount), tmp(m_value));
+ return;
+ }
+ }
+
+ if (isValidForm(opcode, Arg::Tmp, Arg::Tmp, Arg::Tmp)) {
+ append(opcode, tmp(value), tmp(amount), tmp(m_value));
return;
}
+#if CPU(X86)
append(Move, tmp(value), tmp(m_value));
append(Move, tmp(amount), Tmp(X86Registers::ecx));
append(opcode, Tmp(X86Registers::ecx), tmp(m_value));
+#endif
}
template<Air::Opcode opcode32, Air::Opcode opcode64>
@@ -1585,8 +1598,10 @@
case Div: {
if (isInt(m_value->type())) {
+#if CPU(X86)
lowerX86Div();
append(Move, Tmp(X86Registers::eax), tmp(m_value));
+#endif
return;
}
ASSERT(isFloat(m_value->type()));
@@ -1596,8 +1611,10 @@
}
case Mod: {
+#if CPU(X86)
lowerX86Div();
append(Move, Tmp(X86Registers::edx), tmp(m_value));
+#endif
return;
}
@@ -1677,7 +1694,7 @@
}
case BitwiseCast: {
- appendUnOp<MoveInt32ToPacked, Move64ToDouble, MoveDoubleTo64, MovePackedToInt32>(m_value->child(0));
+ appendUnOp<Move32ToFloat, Move64ToDouble, MoveDoubleTo64, MoveFloatTo32>(m_value->child(0));
return;
}
@@ -2151,6 +2168,7 @@
RELEASE_ASSERT_NOT_REACHED();
}
+#if CPU(X86)
void lowerX86Div()
{
Tmp eax = Tmp(X86Registers::eax);
@@ -2176,7 +2194,8 @@
append(convertToDoubleWord, eax, edx);
append(div, eax, edx, tmp(m_value->child(1)));
}
-
+#endif
+
IndexSet<Value> m_locked; // These are values that will have no Tmp in Air.
IndexMap<Value, Tmp> m_valueToTmp; // These are values that must have a Tmp in Air. We say that a Value* with a non-null Tmp is "pinned".
IndexMap<B3::BasicBlock, Air::BasicBlock*> m_blockToBlock;
Modified: trunk/Source/_javascript_Core/b3/air/AirInstInlines.h (194387 => 194388)
--- trunk/Source/_javascript_Core/b3/air/AirInstInlines.h 2015-12-23 10:48:26 UTC (rev 194387)
+++ trunk/Source/_javascript_Core/b3/air/AirInstInlines.h 2015-12-23 11:52:39 UTC (rev 194388)
@@ -167,6 +167,7 @@
return inst.args[0] == Tmp(X86Registers::eax)
&& inst.args[1] == Tmp(X86Registers::edx);
#else
+ UNUSED_PARAM(inst);
return false;
#endif
}
Modified: trunk/Source/_javascript_Core/b3/air/AirOpcode.opcodes (194387 => 194388)
--- trunk/Source/_javascript_Core/b3/air/AirOpcode.opcodes 2015-12-23 10:48:26 UTC (rev 194387)
+++ trunk/Source/_javascript_Core/b3/air/AirOpcode.opcodes 2015-12-23 11:52:39 UTC (rev 194388)
@@ -128,13 +128,19 @@
Imm, Tmp, Tmp
Tmp, Tmp, Tmp
-AddDouble U:F:64, UD:F:64
+arm64: AddDouble U:F:64, U:F:64, D:F:64
+ Tmp, Tmp, Tmp
+
+x86: AddDouble U:F:64, UD:F:64
Tmp, Tmp
- x86: Addr, Tmp
+ Addr, Tmp
-AddFloat U:F:32, UD:F:32
+arm64: AddFloat U:F:32, U:F:32, D:F:32
+ Tmp, Tmp, Tmp
+
+x86: AddFloat U:F:32, UD:F:32
Tmp, Tmp
- x86: Addr, Tmp
+ Addr, Tmp
Sub32 U:G:32, UZD:G:32
Tmp, Tmp
@@ -150,17 +156,23 @@
x86: Addr, Tmp
x86: Tmp, Addr
-SubDouble U:F:64, UD:F:64
+arm64: SubDouble U:F:64, U:F:64, D:F:64
+ Tmp, Tmp, Tmp
+
+x86: SubDouble U:F:64, UD:F:64
Tmp, Tmp
- x86: Addr, Tmp
+ Addr, Tmp
-SubFloat U:F:32, UD:F:32
+arm64: SubFloat U:F:32, U:F:32, D:F:32
+ Tmp, Tmp, Tmp
+
+x86: SubFloat U:F:32, UD:F:32
Tmp, Tmp
- x86: Addr, Tmp
+ Addr, Tmp
Neg32 UZD:G:32
Tmp
- Addr
+ x86: Addr
64: Neg64 UD:G:64
Tmp
@@ -175,21 +187,33 @@
64: Mul64 U:G:64, UD:G:64
Tmp, Tmp
-MulDouble U:F:64, UD:F:64
+arm64: MulDouble U:F:64, U:F:64, D:F:64
+ Tmp, Tmp, Tmp
+
+x86: MulDouble U:F:64, UD:F:64
Tmp, Tmp
- x86: Addr, Tmp
+ Addr, Tmp
-MulFloat U:F:32, UD:F:32
+arm64: MulFloat U:F:32, U:F:32, D:F:32
+ Tmp, Tmp, Tmp
+
+x86: MulFloat U:F:32, UD:F:32
Tmp, Tmp
- x86: Addr, Tmp
+ Addr, Tmp
-DivDouble U:F:32, UD:F:32
+arm64: DivDouble U:F:32, U:F:32, D:F:32
+ Tmp, Tmp, Tmp
+
+x86: DivDouble U:F:32, UD:F:32
Tmp, Tmp
- x86: Addr, Tmp
+ Addr, Tmp
-DivFloat U:F:32, UD:F:32
+arm64: DivFloat U:F:32, U:F:32, D:F:32
+ Tmp, Tmp, Tmp
+
+x86: DivFloat U:F:32, UD:F:32
Tmp, Tmp
- x86: Addr, Tmp
+ Addr, Tmp
x86: X86ConvertToDoubleWord32 U:G:32, ZD:G:32
Tmp*, Tmp*
@@ -203,7 +227,7 @@
x86_64: X86Div64 UZD:G:64, UZD:G:64, U:G:64
Tmp*, Tmp*, Tmp
-Lea UA:G:Ptr, D:G:Ptr
+x86: Lea UA:G:Ptr, D:G:Ptr
Addr, Tmp
And32 U:G:32, UZD:G:32
@@ -217,33 +241,63 @@
Tmp, Tmp
Imm, Tmp
-AndDouble U:F:64, UD:F:64
+arm64: AndDouble U:F:64, U:F:64, D:F:64
+ Tmp, Tmp, Tmp
+
+x86: AndDouble U:F:64, UD:F:64
Tmp, Tmp
-AndFloat U:F:32, UD:F:32
+arm64: AndFloat U:F:32, U:F:32, D:F:32
+ Tmp, Tmp, Tmp
+
+x86: AndFloat U:F:32, UD:F:32
Tmp, Tmp
-Lshift32 U:G:32, UZD:G:32
+arm64: Lshift32 U:G:32, U:G:32, ZD:G:32
+ Tmp, Tmp, Tmp
+ Tmp, Imm, Tmp
+
+x86:Lshift32 U:G:32, UZD:G:32
Tmp*, Tmp
Imm, Tmp
-64: Lshift64 U:G:64, UD:G:64
+arm64: Lshift64 U:G:64, U:G:64, ZD:G:64
+ Tmp, Tmp, Tmp
+ Tmp, Imm, Tmp
+
+x86_64: Lshift64 U:G:64, UD:G:64
Tmp*, Tmp
Imm, Tmp
-Rshift32 U:G:32, UZD:G:32
+arm64: Rshift32 U:G:32, U:G:32, ZD:G:32
+ Tmp, Tmp, Tmp
+ Tmp, Imm, Tmp
+
+x86: Rshift32 U:G:32, UZD:G:32
Tmp*, Tmp
Imm, Tmp
-64: Rshift64 U:G:64, UD:G:64
+arm64: Rshift64 U:G:64, U:G:64, ZD:G:64
+ Tmp, Tmp, Tmp
+ Tmp, Imm, Tmp
+
+x86_64: Rshift64 U:G:64, UD:G:64
Tmp*, Tmp
Imm, Tmp
-Urshift32 U:G:32, UZD:G:32
+arm64: urshift32 U:G:32, U:G:32, ZD:G:32
+ Tmp, Tmp, Tmp
+ Tmp, Imm, Tmp
+
+x86: Urshift32 U:G:32, UZD:G:32
Tmp*, Tmp
Imm, Tmp
-64: Urshift64 U:G:64, UD:G:64
+arm64: Urshift64 U:G:64, U:G:64, ZD:G:64
+ Tmp, Tmp, Tmp
+ Tmp, Imm, Tmp
+
+x86_64: Urshift64 U:G:64, UD:G:64
Tmp*, Tmp
Imm, Tmp
@@ -270,21 +324,27 @@
x86: Tmp, Addr
Imm, Tmp
-Not32 UZD:G:32
+arm64: Not32 U:G:32, ZD:G:32
+ Tmp, Tmp
+
+x86: Not32 UZD:G:32
Tmp
- x86: Addr
+ Addr
-64: Not64 UD:G:64
+arm64: Not64 U:G:64, D:G:64
+ Tmp, Tmp
+
+x86: Not64 UD:G:64
Tmp
- x86: Addr
+ Addr
CeilDouble U:F:64, UD:F:64
Tmp, Tmp
- Addr, Tmp
+ x86: Addr, Tmp
CeilFloat U:F:32, UD:F:32
Tmp, Tmp
- Addr, Tmp
+ x86: Addr, Tmp
SqrtDouble U:F:64, UD:F:64
Tmp, Tmp
@@ -325,27 +385,27 @@
Tmp, Tmp
Imm, Tmp as signExtend32ToPtr
Imm64, Tmp
- Addr, Tmp as loadPtr # This means that "Move Addr, Tmp" is code-generated as "load" not "move".
+ x86: Addr, Tmp as loadPtr # This means that "Move Addr, Tmp" is code-generated as "load" not "move".
Index, Tmp as loadPtr
- Tmp, Addr as storePtr
+ x86: Tmp, Addr as storePtr
Tmp, Index as storePtr
- Imm, Addr as storePtr
+ x86: Imm, Addr as storePtr
Move32 U:G:32, ZD:G:32
Tmp, Tmp as zeroExtend32ToPtr
- Addr, Tmp as load32
+ x86: Addr, Tmp as load32
Index, Tmp as load32
- Tmp, Addr as store32
+ x86: Tmp, Addr as store32
Tmp, Index as store32
- Imm, Addr as store32
- Imm, Index as store32
+ x86: Imm, Addr as store32
+ x86: Imm, Index as store32
SignExtend32ToPtr U:G:32, D:G:Ptr
Tmp, Tmp
ZeroExtend8To32 U:G:8, ZD:G:32
Tmp, Tmp
- Addr, Tmp as load8
+ x86: Addr, Tmp as load8
Index, Tmp as load8
SignExtend8To32 U:G:8, ZD:G:32
@@ -355,26 +415,26 @@
ZeroExtend16To32 U:G:16, ZD:G:32
Tmp, Tmp
- Addr, Tmp as load16
+ x86: Addr, Tmp as load16
Index, Tmp as load16
SignExtend16To32 U:G:16, ZD:G:32
Tmp, Tmp
- Addr, Tmp as load16SignedExtendTo32
+ x86: Addr, Tmp as load16SignedExtendTo32
Index, Tmp as load16SignedExtendTo32
MoveFloat U:F:32, D:F:32
Tmp, Tmp as moveDouble
- Addr, Tmp as loadFloat
+ x86: Addr, Tmp as loadFloat
Index, Tmp as loadFloat
- Tmp, Addr as storeFloat
+ x86: Tmp, Addr as storeFloat
Tmp, Index as storeFloat
MoveDouble U:F:64, D:F:64
Tmp, Tmp
- Addr, Tmp as loadDouble
+ x86: Addr, Tmp as loadDouble
Index, Tmp as loadDouble
- Tmp, Addr as storeDouble
+ x86: Tmp, Addr as storeDouble
Tmp, Index as storeDouble
MoveZeroToDouble D:F:64
@@ -382,44 +442,44 @@
64: Move64ToDouble U:G:64, D:F:64
Tmp, Tmp
- Addr, Tmp as loadDouble
+ x86: Addr, Tmp as loadDouble
Index, Tmp as loadDouble
-MoveInt32ToPacked U:G:32, D:F:32
+Move32ToFloat U:G:32, D:F:32
Tmp, Tmp
- Addr, Tmp as loadFloat
+ x86: Addr, Tmp as loadFloat
Index, Tmp as loadFloat
64: MoveDoubleTo64 U:F:64, D:G:64
Tmp, Tmp
- Addr, Tmp as load64
+ x86: Addr, Tmp as load64
Index, Tmp as load64
-MovePackedToInt32 U:F:32, D:G:32
+MoveFloatTo32 U:F:32, D:G:32
Tmp, Tmp
- Addr, Tmp as load32
+ x86: Addr, Tmp as load32
Index, Tmp as load32
Load8 U:G:8, ZD:G:32
- Addr, Tmp
+ x86: Addr, Tmp
Index, Tmp
Store8 U:G:8, D:G:8
Tmp, Index
- Tmp, Addr
- Imm, Index
- Imm, Addr
+ x86: Tmp, Addr
+ x86: Imm, Index
+ x86: Imm, Addr
Load8SignedExtendTo32 U:G:8, ZD:G:32
- Addr, Tmp
+ x86: Addr, Tmp
Index, Tmp
Load16 U:G:16, ZD:G:32
- Addr, Tmp
+ x86: Addr, Tmp
Index, Tmp
Load16SignedExtendTo32 U:G:16, ZD:G:32
- Addr, Tmp
+ x86: Addr, Tmp
Index, Tmp
Store16 U:G:16, D:G:16
@@ -540,11 +600,11 @@
MoveConditionallyTest32 U:G:32, U:G:32, U:G:32, U:G:Ptr, UD:G:Ptr
ResCond, Tmp, Tmp, Tmp, Tmp
- ResCond, Tmp, Imm, Tmp, Tmp
+ x86: ResCond, Tmp, Imm, Tmp, Tmp
64: MoveConditionallyTest64 U:G:32, U:G:64, U:G:64, U:G:Ptr, UD:G:Ptr
ResCond, Tmp, Tmp, Tmp, Tmp
- ResCond, Tmp, Imm, Tmp, Tmp
+ x86: ResCond, Tmp, Imm, Tmp, Tmp
MoveConditionallyDouble U:G:32, U:F:64, U:F:64, U:G:Ptr, UD:G:Ptr
DoubleCond, Tmp, Tmp, Tmp, Tmp
Modified: trunk/Source/_javascript_Core/jit/AssemblyHelpers.h (194387 => 194388)
--- trunk/Source/_javascript_Core/jit/AssemblyHelpers.h 2015-12-23 10:48:26 UTC (rev 194387)
+++ trunk/Source/_javascript_Core/jit/AssemblyHelpers.h 2015-12-23 11:52:39 UTC (rev 194388)
@@ -436,10 +436,15 @@
move(stackPointerRegister, framePointerRegister);
}
+ void emitFunctionEpilogueWithEmptyFrame()
+ {
+ popPair(framePointerRegister, linkRegister);
+ }
+
void emitFunctionEpilogue()
{
move(framePointerRegister, stackPointerRegister);
- popPair(framePointerRegister, linkRegister);
+ emitFunctionEpilogueWithEmptyFrame();
}
ALWAYS_INLINE void preserveReturnAddressAfterCall(RegisterID reg)
Modified: trunk/Source/_javascript_Core/jit/FPRInfo.h (194387 => 194388)
--- trunk/Source/_javascript_Core/jit/FPRInfo.h 2015-12-23 10:48:26 UTC (rev 194387)
+++ trunk/Source/_javascript_Core/jit/FPRInfo.h 2015-12-23 11:52:39 UTC (rev 194388)
@@ -187,6 +187,7 @@
public:
typedef FPRReg RegisterType;
static const unsigned numberOfRegisters = 23;
+ static const unsigned numberOfArgumentRegisters = 8;
// Temporary registers.
// q8-q15 are callee saved, q31 is use by the MacroAssembler as fpTempRegister.
@@ -258,6 +259,12 @@
return result;
}
+ static FPRReg toArgumentRegister(unsigned index)
+ {
+ ASSERT(index < 8);
+ return static_cast<FPRReg>(index);
+ }
+
static const char* debugName(FPRReg reg)
{
ASSERT(reg != InvalidFPRReg);
