No. It is still an open question how best to implement atomic and when in X10.
The spec allows weak atomicity, so many avenues are open. The current implementation is 1 lock per place. On Fri, Feb 11, 2011 at 10:54 AM, Aditya Sriram M < aditya.mattapar...@iiitb.org> wrote: > Hi, > > > > Does X10 have any STM implementation as of now? Is there a good reference > of > the features? > > > > Pls let us know. > > > > Thanks, > > Aditya > > > ------------------------------------------------------------------------------ > The ultimate all-in-one performance toolkit: Intel(R) Parallel Studio XE: > Pinpoint memory and threading errors before they happen. > Find and fix more than 250 security defects in the development cycle. > Locate bottlenecks in serial and parallel code that limit performance. > http://p.sf.net/sfu/intel-dev2devfeb > _______________________________________________ > X10-users mailing list > X10-users@lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/x10-users > ------------------------------------------------------------------------------ The ultimate all-in-one performance toolkit: Intel(R) Parallel Studio XE: Pinpoint memory and threading errors before they happen. Find and fix more than 250 security defects in the development cycle. Locate bottlenecks in serial and parallel code that limit performance. http://p.sf.net/sfu/intel-dev2devfeb _______________________________________________ X10-users mailing list X10-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/x10-users
