Hi,

I'm a student working with Andreas.
This isn't only a problem of buffered output as you supposed. The output of the 
following code is mixed up the same way as the prior one. Indeed, it seems a "a 
little less" mixed up, but is still not working as expected.

public class Clockbug {

    public static def main(args: Array[String]) {

        val runs : Int = 10;

        val output : ArrayList[String] = new ArrayList[String]();
        val outputRef = GlobalRef[ArrayList[String]](output);

        clocked finish {
            for (place in Place.places())  at (place)  {
                clocked async  {
                    for (var i : Int = 0; i < runs; i++) {
                        val message1 = "Phase A at place " + here.id + " in 
run:" + i;
                        at(outputRef) {
                            atomic { outputRef().add(message1); }
                        }
                        Clock.advanceAll();

                        val message2 = "Phase B at place " + here.id + " in 
run:" + i;
                        at(outputRef) {
                            atomic { outputRef().add(message2); }
                        }
                        Clock.advanceAll();
                    }
                }}}
        for(s in output) {
            Console.OUT.println(s);
        }
    }
}

This code produces output such as: 

Phase B at place 2 in run:8
Phase A at place 3 in run:8
Phase B at place 0 in run:8
Phase A at place 1 in run:8
Phase A at place 2 in run:9
Phase B at place 3 in run:8
Phase A at place 0 in run:9
Phase B at place 1 in run:8
Phase B at place 2 in run:9
Phase A at place 3 in run:9
Phase B at place 0 in run:9
Phase A at place 1 in run:9
Phase B at place 3 in run:9
Phase B at place 1 in run:9

As you can see, the runs are still mixed up, let alone the phases. It seems to 
get worse with every iterations of the loop. It would be great if you could 
help.

Dominic

________________________________________
Von: Olivier Tardieu [tard...@us.ibm.com]
Gesendet: Freitag, 4. Mai 2012 21:02
An: Mailing list for users of the X10 programming language
Betreff: Re: [X10-users] Clock bug?

Hi,

I think you are expecting outputs from distinct places to show in order.
There is no such guarantee.

You code guarantees that Console.OUT.println(...) in phase A at place 1 will 
happen before Console.OUT.printn(...) in phase B at place 0.
But the messages may appear on the console in a different order (as they take 
time to travel across places).

Olivier

[cid:1__=0abbf367dff501ab8f9e8a93df...@us.ibm.com]Andreas Zwinkau ---05/04/2012 
03:07:54 AM--------BEGIN PGP SIGNED MESSAGE----- Hash: SHA1

From: Andreas Zwinkau <zwin...@kit.edu>
To: x10-users@lists.sourceforge.net,
Date: 05/04/2012 03:07 AM
Subject: [X10-users] Clock bug?

________________________________



-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

The following program is not synchronized as I expect it to be:

public class Clockbug {
 public static def main(args: Array[String]) {
   val runs = 7;
   clocked finish {
     for (place in Place.places())  at (place) {
       clocked async  {
         for (var i : Int = 0; i < runs; i++) {
           atomic Console.OUT.println("Run "+i+" phase A at place " +
here.id);
           Clock.advanceAll();
           atomic Console.OUT.println("Run "+i+" phase B at place " +
here.id);
           Clock.advanceAll();
}}}}}}

For each iteration i, the "phase A" output should appear before the
"phase B" output. However, I also observe output like this:

$ X10_NPLACES=4 ./a.out
Run 0 phase A at place 2
Run 0 phase A at place 0
Run 0 phase A at place 1
Run 0 phase A at place 3
Run 0 phase B at place 0
Run 0 phase B at place 2
Run 0 phase B at place 1
Run 1 phase A at place 2
Run 0 phase B at place 3
Run 1 phase A at place 0
Run 1 phase A at place 1
Run 1 phase A at place 3
Run 1 phase B at place 2
Run 1 phase B at place 0
Run 1 phase B at place 1
Run 1 phase B at place 3

Apparently, the iterations get mixed up. Is that a bug in Clock?

- --
Andreas Zwinkau

Karlsruhe Institute of Technology (KIT)
Institut für Programmstrukturen und Datenorganisation (IPD)
Lehrstuhl Prof. Snelting
Adenauerring 20a
76131 Karlsruhe

Phone:  +49 721 608 48351
Fax:    +49 721 608 48457
Email:  zwin...@kit.edu
Web:    http://pp.info.uni-karlsruhe.de/person.php?id=107

KIT – University of the State of Baden-Wuerttemberg and
National Research Center of the Helmholtz Association
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