# HG changeset patch # User Murugan Vairavel <[email protected]> # Date 1384153358 -19800 # Mon Nov 11 12:32:38 2013 +0530 # Node ID c4c017171fb8ef6c30eb93b61fee9e5bdc02ff71 # Parent a4f6d60ab5db6b8ee2a8f2f764650c07fc606026 asm: pixelsub_ps routine for 32xN block
diff -r a4f6d60ab5db -r c4c017171fb8 source/common/x86/pixel-a.asm --- a/source/common/x86/pixel-a.asm Mon Nov 11 11:38:40 2013 +0530 +++ b/source/common/x86/pixel-a.asm Mon Nov 11 12:32:38 2013 +0530 @@ -5858,3 +5858,88 @@ %endmacro PIXELSUB_PS_W24_H2 24, 32 + +;----------------------------------------------------------------------------- +; void pixel_sub_ps_c_%1x%2(pixel *dest, intptr_t destride, pixel *src0, pixel *src1, intptr_t srcstride0, intptr_t srcstride1); +;----------------------------------------------------------------------------- +%macro PIXELSUB_PS_W32_H2 2 +INIT_XMM sse4 +cglobal pixel_sub_ps_%1x%2, 6, 7, 8, dest, deststride, src0, src1, srcstride0, srcstride1 + +add r1, r1 +mov r6d, %2/2 + +.loop + + movh m0, [r2] + movh m1, [r2 + 8] + movh m2, [r2 + 16] + movh m3, [r2 + 24] + movh m4, [r3] + movh m5, [r3 + 8] + movh m6, [r3 + 16] + movh m7, [r3 + 24] + + pmovzxbw m0, m0 + pmovzxbw m1, m1 + pmovzxbw m2, m2 + pmovzxbw m3, m3 + pmovzxbw m4, m4 + pmovzxbw m5, m5 + pmovzxbw m6, m6 + pmovzxbw m7, m7 + + psubw m0, m4 + psubw m1, m5 + psubw m2, m6 + psubw m3, m7 + + movu [r0], m0 + movu [r0 + 16], m1 + movu [r0 + 32], m2 + movu [r0 + 48], m3 + + movh m0, [r2 + r4] + movh m1, [r2 + r4 + 8] + movh m2, [r2 + r4 + 16] + movh m3, [r2 + r4 + 24] + movh m4, [r3 + r5] + movh m5, [r3 + r5 + 8] + movh m6, [r3 + r5 + 16] + movh m7, [r3 + r5 + 24] + + pmovzxbw m0, m0 + pmovzxbw m1, m1 + pmovzxbw m2, m2 + pmovzxbw m3, m3 + pmovzxbw m4, m4 + pmovzxbw m5, m5 + pmovzxbw m6, m6 + pmovzxbw m7, m7 + + psubw m0, m4 + psubw m1, m5 + psubw m2, m6 + psubw m3, m7 + + movu [r0 + r1], m0 + movu [r0 + r1 + 16], m1 + movu [r0 + r1 + 32], m2 + movu [r0 + r1 + 48], m3 + + lea r2, [r2 + 2 * r4] + lea r3, [r3 + 2 * r5] + lea r0, [r0 + 2 * r1] + + dec r6d + +jnz .loop + +RET +%endmacro + +PIXELSUB_PS_W32_H2 32, 8 +PIXELSUB_PS_W32_H2 32, 16 +PIXELSUB_PS_W32_H2 32, 24 +PIXELSUB_PS_W32_H2 32, 32 +PIXELSUB_PS_W32_H2 32, 64 _______________________________________________ x265-devel mailing list [email protected] https://mailman.videolan.org/listinfo/x265-devel
