At 2015-03-04 14:53:16,"Divya Manivannan" <[email protected]> wrote: ># HG changeset patch ># User Divya Manivannan <[email protected]> ># Date 1425451946 -19800 ># Wed Mar 04 12:22:26 2015 +0530 ># Node ID 339e62f4eb0610e5589965508933c8f87f56ec16 ># Parent 526974a41de7f30f53375a9583ddb3320384cd7f >asm-avx2: filter_vpp[32x24, 32x16, 32x8], filter_vps[32x24, 32x16, 32x8] > >filter_vpp[32x24, 32x16, 32x8]: 2848c->1489c, 1904c->1048c, 1015c->576c >filter_vps[32x24, 32x16, 32x8]: 2836c->1844c, 2043c->1280c, 1003c->720c > >diff -r 526974a41de7 -r 339e62f4eb06 source/common/x86/asm-primitives.cpp >--- a/source/common/x86/asm-primitives.cpp Wed Mar 04 11:49:20 2015 +0530 >+++ b/source/common/x86/asm-primitives.cpp Wed Mar 04 12:22:26 2015 +0530 >@@ -1583,9 +1583,15 @@ > > p.chroma[X265_CSP_I420].pu[CHROMA_420_16x16].filter_vpp = > x265_interp_4tap_vert_pp_16x16_avx2; > p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_vpp = > x265_interp_4tap_vert_pp_32x32_avx2; >+ p.chroma[X265_CSP_I420].pu[CHROMA_420_32x24].filter_vpp = >x265_interp_4tap_vert_pp_32x24_avx2; >+ p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_vpp = >x265_interp_4tap_vert_pp_32x16_avx2; >+ p.chroma[X265_CSP_I420].pu[CHROMA_420_32x8].filter_vpp = >x265_interp_4tap_vert_pp_32x8_avx2; > > p.chroma[X265_CSP_I420].pu[CHROMA_420_16x16].filter_vps = > x265_interp_4tap_vert_ps_16x16_avx2; > p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_vps = > x265_interp_4tap_vert_ps_32x32_avx2; >+ p.chroma[X265_CSP_I420].pu[CHROMA_420_32x24].filter_vps = >x265_interp_4tap_vert_ps_32x24_avx2; >+ p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_vps = >x265_interp_4tap_vert_ps_32x16_avx2; >+ p.chroma[X265_CSP_I420].pu[CHROMA_420_32x8].filter_vps = >x265_interp_4tap_vert_ps_32x8_avx2; > #else > /* functions with both 64-bit and 32-bit implementations */ > p.cu[BLOCK_4x4].dct = x265_dct4_avx2; >diff -r 526974a41de7 -r 339e62f4eb06 source/common/x86/ipfilter8.asm >--- a/source/common/x86/ipfilter8.asm Wed Mar 04 11:49:20 2015 +0530 >+++ b/source/common/x86/ipfilter8.asm Wed Mar 04 12:22:26 2015 +0530 >@@ -5230,10 +5230,10 @@ > FILTER_V4_W32 32, 48 > FILTER_V4_W32 32, 64 > >-%macro FILTER_VER_CHROMA_AVX2_32x32 1 >+%macro FILTER_VER_CHROMA_AVX2_32xN 2 > INIT_YMM avx2 > %if ARCH_X86_64 == 1 >-cglobal interp_4tap_vert_%1_32x32, 4, 7, 13 >+cglobal interp_4tap_vert_%1_32x%2, 4, 7, 13 > mov r4d, r4m > shl r4d, 6 > >@@ -5252,10 +5252,10 @@ > mova m12, [pw_512] > %else > add r3d, r3d >- vbroadcasti128 m12, [pw_2000] >+ mova m12, [pw_2000] both instruction is right, we choice it depends on IACA analyze report
> %endif > lea r5, [r3 * 3] >- mov r6d, 8 >+ mov r6d, %2 / 4 > .loopW: > movu m0, [r0] ; m0 = row 0 > movu m1, [r0 + r1] ; m1 = row 1 >@@ -5362,8 +5362,14 @@ > %endif > %endmacro > >-FILTER_VER_CHROMA_AVX2_32x32 pp >-FILTER_VER_CHROMA_AVX2_32x32 ps >+FILTER_VER_CHROMA_AVX2_32xN pp, 32 >+FILTER_VER_CHROMA_AVX2_32xN pp, 24 >+FILTER_VER_CHROMA_AVX2_32xN pp, 16 >+FILTER_VER_CHROMA_AVX2_32xN pp, 8 >+FILTER_VER_CHROMA_AVX2_32xN ps, 32 >+FILTER_VER_CHROMA_AVX2_32xN ps, 24 >+FILTER_VER_CHROMA_AVX2_32xN ps, 16 >+FILTER_VER_CHROMA_AVX2_32xN ps, 8 > > ;----------------------------------------------------------------------------- > ; void interp_4tap_vert_pp_%1x%2(pixel *src, intptr_t srcStride, pixel *dst, > intptr_t dstStride, int coeffIdx) >_______________________________________________ >x265-devel mailing list >[email protected] >https://mailman.videolan.org/listinfo/x265-devel
_______________________________________________ x265-devel mailing list [email protected] https://mailman.videolan.org/listinfo/x265-devel
