right
At 2015-03-12 20:02:20,"Divya Manivannan" <[email protected]> wrote: ># HG changeset patch ># User Divya Manivannan <[email protected]> ># Date 1426161705 -19800 ># Thu Mar 12 17:31:45 2015 +0530 ># Node ID 17d37a2b315c4ead360461e7ce3dfd86d4b21287 ># Parent 45d498a1a59263fd758bf71c910e7d4289e771d3 >asm: filter_vsp[16x32, 24x32, 32x32], filter_vss[16x32, 24x32, 32x32] in avx2 > >filter_vsp[16x32, 24x32, 32x32]: 6015c->3693c, 8710c->5692c, 11284c->7731c >filter_vss[16x32, 24x32, 32x32]: 4702c->4024c, 7013c->6132c, 9046c->7926c > >diff -r 45d498a1a592 -r 17d37a2b315c source/common/x86/asm-primitives.cpp >--- a/source/common/x86/asm-primitives.cpp Thu Mar 12 16:55:03 2015 +0530 >+++ b/source/common/x86/asm-primitives.cpp Thu Mar 12 17:31:45 2015 +0530 >@@ -1625,11 +1625,17 @@ > p.chroma[X265_CSP_I420].pu[CHROMA_420_4x4].filter_vsp = > x265_interp_4tap_vert_sp_4x4_avx2; > p.chroma[X265_CSP_I420].pu[CHROMA_420_8x8].filter_vsp = > x265_interp_4tap_vert_sp_8x8_avx2; > p.chroma[X265_CSP_I420].pu[CHROMA_420_16x16].filter_vsp = > x265_interp_4tap_vert_sp_16x16_avx2; >+ p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_vsp = >x265_interp_4tap_vert_sp_32x32_avx2; >+ p.chroma[X265_CSP_I420].pu[CHROMA_420_16x32].filter_vsp = >x265_interp_4tap_vert_sp_16x32_avx2; >+ p.chroma[X265_CSP_I420].pu[CHROMA_420_24x32].filter_vsp = >x265_interp_4tap_vert_sp_24x32_avx2; > p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_vsp = > x265_interp_4tap_vert_sp_32x16_avx2; > > p.chroma[X265_CSP_I420].pu[CHROMA_420_4x4].filter_vss = > x265_interp_4tap_vert_ss_4x4_avx2; > p.chroma[X265_CSP_I420].pu[CHROMA_420_8x8].filter_vss = > x265_interp_4tap_vert_ss_8x8_avx2; > p.chroma[X265_CSP_I420].pu[CHROMA_420_16x16].filter_vss = > x265_interp_4tap_vert_ss_16x16_avx2; >+ p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_vss = >x265_interp_4tap_vert_ss_32x32_avx2; >+ p.chroma[X265_CSP_I420].pu[CHROMA_420_16x32].filter_vss = >x265_interp_4tap_vert_ss_16x32_avx2; >+ p.chroma[X265_CSP_I420].pu[CHROMA_420_24x32].filter_vss = >x265_interp_4tap_vert_ss_24x32_avx2; > p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_vss = > x265_interp_4tap_vert_ss_32x16_avx2; > } > #endif >diff -r 45d498a1a592 -r 17d37a2b315c source/common/x86/ipfilter8.asm >--- a/source/common/x86/ipfilter8.asm Thu Mar 12 16:55:03 2015 +0530 >+++ b/source/common/x86/ipfilter8.asm Thu Mar 12 17:31:45 2015 +0530 >@@ -12220,6 +12220,60 @@ > FILTER_VER_CHROMA_S_AVX2_Nx16 ss, 16 > FILTER_VER_CHROMA_S_AVX2_Nx16 ss, 32 > >+%macro FILTER_VER_CHROMA_S_AVX2_NxN 3 >+INIT_YMM avx2 >+%if ARCH_X86_64 == 1 >+cglobal interp_4tap_vert_%3_%1x%2, 4, 11, 10 >+ mov r4d, r4m >+ shl r4d, 6 >+ add r1d, r1d >+ >+%ifdef PIC >+ lea r5, [pw_ChromaCoeffV] >+ add r5, r4 >+%else >+ lea r5, [pw_ChromaCoeffV + r4] >+%endif >+ lea r4, [r1 * 3] >+ sub r0, r1 >+%ifidn %3,sp >+ mova m9, [pd_526336] >+%else >+ add r3d, r3d >+%endif >+ lea r6, [r3 * 3] >+ mov r9d, %2 / 16 >+.loopH: >+ mov r10d, %1 / 8 >+.loopW: >+ PROCESS_CHROMA_S_AVX2_W8_16R %3 >+%ifidn %3,sp >+ add r2, 8 >+%else >+ add r2, 16 >+%endif >+ add r0, 16 >+ dec r10d >+ jnz .loopW >+ lea r0, [r7 - 2 * %1 + 16] >+%ifidn %3,sp >+ lea r2, [r8 + r3 * 4 - %1 + 8] >+%else >+ lea r2, [r8 + r3 * 4 - 2 * %1 + 16] >+%endif >+ dec r9d >+ jnz .loopH >+ RET >+%endif >+%endmacro >+ >+FILTER_VER_CHROMA_S_AVX2_NxN 16, 32, sp >+FILTER_VER_CHROMA_S_AVX2_NxN 24, 32, sp >+FILTER_VER_CHROMA_S_AVX2_NxN 32, 32, sp >+FILTER_VER_CHROMA_S_AVX2_NxN 16, 32, ss >+FILTER_VER_CHROMA_S_AVX2_NxN 24, 32, ss >+FILTER_VER_CHROMA_S_AVX2_NxN 32, 32, ss >+ > ;--------------------------------------------------------------------------------------------------------------------- > ; void interp_4tap_vertical_ss_%1x%2(int16_t *src, intptr_t srcStride, > int16_t *dst, intptr_t dstStride, int coeffIdx) > ;--------------------------------------------------------------------------------------------------------------------- >_______________________________________________ >x265-devel mailing list >[email protected] >https://mailman.videolan.org/listinfo/x265-devel
_______________________________________________ x265-devel mailing list [email protected] https://mailman.videolan.org/listinfo/x265-devel
