# HG changeset patch
# User Vignesh Vijayakumar
# Date 1500260234 -19800
#      Mon Jul 17 08:27:14 2017 +0530
# Node ID 229c13a0d7e4a1dafad7b0a2e9eef041ecccdb77
# Parent  5a2d94db6fcaabf532f00848a72fa337bb5e65ac
x86: AVX512 pixel_sad_x3_48x64

AVX2 performance :  59.91x
AVX512 performance: 61.95x

diff -r 5a2d94db6fca -r 229c13a0d7e4 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp      Sun Jul 16 18:05:11 2017 +0530
+++ b/source/common/x86/asm-primitives.cpp      Mon Jul 17 08:27:14 2017 +0530
@@ -3745,6 +3745,7 @@
         p.pu[LUMA_64x32].sad_x3 = PFX(pixel_sad_x3_64x32_avx512);
         p.pu[LUMA_64x48].sad_x3 = PFX(pixel_sad_x3_64x48_avx512);
         p.pu[LUMA_64x64].sad_x3 = PFX(pixel_sad_x3_64x64_avx512);
+        p.pu[LUMA_48x64].sad_x3 = PFX(pixel_sad_x3_48x64_avx512);
 
         p.pu[LUMA_32x32].sad_x4 = PFX(pixel_sad_x4_32x32_avx512);
         p.pu[LUMA_32x16].sad_x4 = PFX(pixel_sad_x4_32x16_avx512);
diff -r 5a2d94db6fca -r 229c13a0d7e4 source/common/x86/sad-a.asm
--- a/source/common/x86/sad-a.asm       Sun Jul 16 18:05:11 2017 +0530
+++ b/source/common/x86/sad-a.asm       Mon Jul 17 08:27:14 2017 +0530
@@ -6306,6 +6306,125 @@
     paddd           m2, m3
 %endmacro
 
+%macro SAD_X3_48x8_AVX512 0
+    movu            ym3, [r0]
+    vinserti32x8    m3, [r0 + FENC_STRIDE], 1
+    movu            ym4, [r1]
+    vinserti32x8    m4, [r1 + r4], 1
+    movu            ym5, [r2]
+    vinserti32x8    m5, [r2 + r4], 1
+    movu            ym6, [r3]
+    vinserti32x8    m6, [r3 + r4], 1
+
+    psadbw          m7, m3, m4
+    paddd           m0, m7
+    psadbw          m4, m3, m5
+    paddd           m1, m4
+    psadbw          m3, m6
+    paddd           m2, m3
+
+    movu            ym3, [r0 + FENC_STRIDE * 2]
+    vinserti32x8     m3, [r0 + FENC_STRIDE * 3], 1
+    movu            ym4, [r1 + r4 * 2]
+    vinserti32x8     m4, [r1 + r6], 1
+    movu            ym5, [r2 + r4 * 2]
+    vinserti32x8     m5, [r2 + r6], 1
+    movu            ym6, [r3 + r4 * 2]
+    vinserti32x8     m6, [r3 + r6], 1
+
+    psadbw          m7, m3, m4
+    paddd           m0, m7
+    psadbw          m4, m3, m5
+    paddd           m1, m4
+    psadbw          m3, m6
+    paddd           m2, m3
+
+    movu           xm3, [r0 + 32]
+    vinserti32x4    m3, [r0 + FENC_STRIDE + 32], 1
+    vinserti32x4    m3, [r0 + 2 * FENC_STRIDE + 32], 2
+    vinserti32x4    m3, [r0 + 3 * FENC_STRIDE + 32], 3
+    movu           xm4, [r1 + 32]
+    vinserti32x4    m4, [r1 + r4 + 32], 1
+    vinserti32x4    m4, [r1 + 2 * r4 + 32], 2
+    vinserti32x4    m4, [r1 + r6 + 32], 3
+    movu           xm5, [r2 + 32]
+    vinserti32x4    m5, [r2 + r4 + 32], 1
+    vinserti32x4    m5, [r2 + 2 * r4 + 32], 2
+    vinserti32x4    m5, [r2 + r6 + 32], 3
+    movu           xm6, [r3 + 32]
+    vinserti32x4    m6, [r3 + r4 + 32], 1
+    vinserti32x4    m6, [r3 + 2 * r4 + 32], 2
+    vinserti32x4    m6, [r3 + r6 + 32], 3
+
+    psadbw          m7, m3, m4
+    paddd           m0, m7
+    psadbw          m4, m3, m5
+    paddd           m1, m4
+    psadbw          m3, m6
+    paddd           m2, m3
+
+    add             r0, FENC_STRIDE * 4
+    lea             r1, [r1 + r4 * 4]
+    lea             r2, [r2 + r4 * 4]
+    lea             r3, [r3 + r4 * 4]
+
+    movu            ym3, [r0]
+    vinserti32x8    m3, [r0 + FENC_STRIDE], 1
+    movu            ym4, [r1]
+    vinserti32x8    m4, [r1 + r4], 1
+    movu            ym5, [r2]
+    vinserti32x8    m5, [r2 + r4], 1
+    movu            ym6, [r3]
+    vinserti32x8    m6, [r3 + r4], 1
+
+    psadbw          m7, m3, m4
+    paddd           m0, m7
+    psadbw          m4, m3, m5
+    paddd           m1, m4
+    psadbw          m3, m6
+    paddd           m2, m3
+
+    movu            ym3, [r0 + FENC_STRIDE * 2]
+    vinserti32x8     m3, [r0 + FENC_STRIDE * 3], 1
+    movu            ym4, [r1 + r4 * 2]
+    vinserti32x8     m4, [r1 + r6], 1
+    movu            ym5, [r2 + r4 * 2]
+    vinserti32x8     m5, [r2 + r6], 1
+    movu            ym6, [r3 + r4 * 2]
+    vinserti32x8     m6, [r3 + r6], 1
+
+    psadbw          m7, m3, m4
+    paddd           m0, m7
+    psadbw          m4, m3, m5
+    paddd           m1, m4
+    psadbw          m3, m6
+    paddd           m2, m3
+
+    movu           xm3, [r0 + 32]
+    vinserti32x4    m3, [r0 + FENC_STRIDE + 32], 1
+    vinserti32x4    m3, [r0 + 2 * FENC_STRIDE + 32], 2
+    vinserti32x4    m3, [r0 + 3 * FENC_STRIDE + 32], 3
+    movu           xm4, [r1 + 32]
+    vinserti32x4    m4, [r1 + r4 + 32], 1
+    vinserti32x4    m4, [r1 + 2 * r4 + 32], 2
+    vinserti32x4    m4, [r1 + r6 + 32], 3
+    movu           xm5, [r2 + 32]
+    vinserti32x4    m5, [r2 + r4 + 32], 1
+    vinserti32x4    m5, [r2 + 2 * r4 + 32], 2
+    vinserti32x4    m5, [r2 + r6 + 32], 3
+    movu           xm6, [r3 + 32]
+    vinserti32x4    m6, [r3 + r4 + 32], 1
+    vinserti32x4    m6, [r3 + 2 * r4 + 32], 2
+    vinserti32x4    m6, [r3 + r6 + 32], 3
+
+    psadbw          m7, m3, m4
+    paddd           m0, m7
+    psadbw          m4, m3, m5
+    paddd           m1, m4
+    psadbw          m3, m6
+    paddd           m2, m3
+%endmacro
+
 %macro PIXEL_SAD_X3_END_AVX512 0
     vextracti32x8   ym3, m0, 1
     vextracti32x8   ym4, m1, 1
@@ -6573,6 +6692,52 @@
     SAD_X3_32x8_AVX512
     PIXEL_SAD_X3_END_AVX512
     RET
+
+INIT_ZMM avx512
+cglobal pixel_sad_x3_48x64, 6,7,8
+    pxor            m0, m0
+    pxor            m1, m1
+    pxor            m2, m2
+    lea             r6, [r4 * 3]
+
+    SAD_X3_48x8_AVX512
+    add             r0, FENC_STRIDE * 4
+    lea             r1, [r1 + r4 * 4]
+    lea             r2, [r2 + r4 * 4]
+    lea             r3, [r3 + r4 * 4]
+    SAD_X3_48x8_AVX512
+    add             r0, FENC_STRIDE * 4
+    lea             r1, [r1 + r4 * 4]
+    lea             r2, [r2 + r4 * 4]
+    lea             r3, [r3 + r4 * 4]
+    SAD_X3_48x8_AVX512
+    add             r0, FENC_STRIDE * 4
+    lea             r1, [r1 + r4 * 4]
+    lea             r2, [r2 + r4 * 4]
+    lea             r3, [r3 + r4 * 4]
+    SAD_X3_48x8_AVX512
+    add             r0, FENC_STRIDE * 4
+    lea             r1, [r1 + r4 * 4]
+    lea             r2, [r2 + r4 * 4]
+    lea             r3, [r3 + r4 * 4]
+    SAD_X3_48x8_AVX512
+    add             r0, FENC_STRIDE * 4
+    lea             r1, [r1 + r4 * 4]
+    lea             r2, [r2 + r4 * 4]
+    lea             r3, [r3 + r4 * 4]
+    SAD_X3_48x8_AVX512
+    add             r0, FENC_STRIDE * 4
+    lea             r1, [r1 + r4 * 4]
+    lea             r2, [r2 + r4 * 4]
+    lea             r3, [r3 + r4 * 4]
+    SAD_X3_48x8_AVX512
+    add             r0, FENC_STRIDE * 4
+    lea             r1, [r1 + r4 * 4]
+    lea             r2, [r2 + r4 * 4]
+    lea             r3, [r3 + r4 * 4]
+    SAD_X3_48x8_AVX512
+    PIXEL_SAD_X3_END_AVX512
+    RET
 ;------------------------------------------------------------
 ;sad_x3 avx512 code end
 ;------------------------------------------------------------
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