# HG changeset patch
# User Vignesh Vijayakumar<vign...@multicorewareinc.com>
# Date 1510029383 -19800
#      Tue Nov 07 10:06:23 2017 +0530
# Node ID c983858deccb26e5b4c957fbff959c1e74f84756
# Parent  0775ffcdfc8a0c4ad078e8c4197f6bff7158efd8
x86: AVX512 interp_4tap_vert_ps_32xN for high bit depth

i444
Size  |  AVX2 performance | AVX512 performance
----------------------------------------------
32x8  |      26.31x       |      43.62x
32x16 |      27.04x       |      45.52x
32x24 |      27.33x       |      43.80x
32x32 |      27.64x       |      44.25x
32x64 |      27.89x       |      44.69x

diff -r 0775ffcdfc8a -r c983858deccb source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp      Mon Nov 06 15:41:43 2017 +0530
+++ b/source/common/x86/asm-primitives.cpp      Tue Nov 07 10:06:23 2017 +0530
@@ -2645,6 +2645,11 @@
         p.chroma[X265_CSP_I444].pu[LUMA_32x24].filter_vpp = 
PFX(interp_4tap_vert_pp_32x24_avx512);
         p.chroma[X265_CSP_I444].pu[LUMA_32x32].filter_vpp = 
PFX(interp_4tap_vert_pp_32x32_avx512);
         p.chroma[X265_CSP_I444].pu[LUMA_32x64].filter_vpp = 
PFX(interp_4tap_vert_pp_32x64_avx512);
+        p.chroma[X265_CSP_I444].pu[LUMA_32x8].filter_vps = 
PFX(interp_4tap_vert_ps_32x8_avx512);
+        p.chroma[X265_CSP_I444].pu[LUMA_32x16].filter_vps = 
PFX(interp_4tap_vert_ps_32x16_avx512);
+        p.chroma[X265_CSP_I444].pu[LUMA_32x24].filter_vps = 
PFX(interp_4tap_vert_ps_32x24_avx512);
+        p.chroma[X265_CSP_I444].pu[LUMA_32x32].filter_vps = 
PFX(interp_4tap_vert_ps_32x32_avx512);
+        p.chroma[X265_CSP_I444].pu[LUMA_32x64].filter_vps = 
PFX(interp_4tap_vert_ps_32x64_avx512);
         p.chroma[X265_CSP_I444].pu[LUMA_16x4].filter_vpp = 
PFX(interp_4tap_vert_pp_16x4_avx512);
         p.chroma[X265_CSP_I444].pu[LUMA_16x8].filter_vpp = 
PFX(interp_4tap_vert_pp_16x8_avx512);
         p.chroma[X265_CSP_I444].pu[LUMA_16x12].filter_vpp = 
PFX(interp_4tap_vert_pp_16x12_avx512);
@@ -2659,6 +2664,10 @@
         p.chroma[X265_CSP_I422].pu[CHROMA_422_32x32].filter_vpp = 
PFX(interp_4tap_vert_pp_32x32_avx512);
         p.chroma[X265_CSP_I422].pu[CHROMA_422_32x48].filter_vpp = 
PFX(interp_4tap_vert_pp_32x48_avx512);
         p.chroma[X265_CSP_I422].pu[CHROMA_422_32x64].filter_vpp = 
PFX(interp_4tap_vert_pp_32x64_avx512);
+        p.chroma[X265_CSP_I422].pu[CHROMA_422_32x16].filter_vps = 
PFX(interp_4tap_vert_ps_32x16_avx512);
+        p.chroma[X265_CSP_I422].pu[CHROMA_422_32x32].filter_vps = 
PFX(interp_4tap_vert_ps_32x32_avx512);
+        p.chroma[X265_CSP_I422].pu[CHROMA_422_32x48].filter_vps = 
PFX(interp_4tap_vert_ps_32x48_avx512);
+        p.chroma[X265_CSP_I422].pu[CHROMA_422_32x64].filter_vps = 
PFX(interp_4tap_vert_ps_32x64_avx512);
         p.chroma[X265_CSP_I422].pu[CHROMA_422_16x8].filter_vpp = 
PFX(interp_4tap_vert_pp_16x8_avx512);
         p.chroma[X265_CSP_I422].pu[CHROMA_422_16x16].filter_vpp = 
PFX(interp_4tap_vert_pp_16x16_avx512);
         p.chroma[X265_CSP_I422].pu[CHROMA_422_16x24].filter_vpp = 
PFX(interp_4tap_vert_pp_16x24_avx512);
@@ -2673,6 +2682,10 @@
         p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_vpp = 
PFX(interp_4tap_vert_pp_32x16_avx512);
         p.chroma[X265_CSP_I420].pu[CHROMA_420_32x24].filter_vpp = 
PFX(interp_4tap_vert_pp_32x24_avx512);
         p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_vpp = 
PFX(interp_4tap_vert_pp_32x32_avx512);
+        p.chroma[X265_CSP_I420].pu[CHROMA_420_32x8].filter_vps = 
PFX(interp_4tap_vert_ps_32x8_avx512);
+        p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_vps = 
PFX(interp_4tap_vert_ps_32x16_avx512);
+        p.chroma[X265_CSP_I420].pu[CHROMA_420_32x24].filter_vps = 
PFX(interp_4tap_vert_ps_32x24_avx512);
+        p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_vps = 
PFX(interp_4tap_vert_ps_32x32_avx512);
         p.chroma[X265_CSP_I420].pu[CHROMA_420_16x4].filter_vpp = 
PFX(interp_4tap_vert_pp_16x4_avx512);
         p.chroma[X265_CSP_I420].pu[CHROMA_420_16x8].filter_vpp = 
PFX(interp_4tap_vert_pp_16x8_avx512);
         p.chroma[X265_CSP_I420].pu[CHROMA_420_16x12].filter_vpp = 
PFX(interp_4tap_vert_pp_16x12_avx512);
diff -r 0775ffcdfc8a -r c983858deccb source/common/x86/ipfilter16.asm
--- a/source/common/x86/ipfilter16.asm  Mon Nov 06 15:41:43 2017 +0530
+++ b/source/common/x86/ipfilter16.asm  Tue Nov 07 10:06:23 2017 +0530
@@ -7341,6 +7341,88 @@
     jnz             .loop
     RET
 %endif
+
+%macro PROCESS_CHROMA_VERT_PS_32x2_AVX512 0
+    movu                  m1,                 [r0]
+    movu                  m3,                 [r0 + r1]
+    punpcklwd             m0,                 m1,                  m3
+    pmaddwd               m0,                 [r5]
+    punpckhwd             m1,                 m3
+    pmaddwd               m1,                 [r5]
+
+    movu                  m4,                 [r0 + 2 * r1]
+    punpcklwd             m2,                 m3,                  m4
+    pmaddwd               m2,                 [r5]
+    punpckhwd             m3,                 m4
+    pmaddwd               m3,                 [r5]
+
+    lea                   r0,                 [r0 + 2 * r1]
+    movu                  m5,                 [r0 + r1]
+    punpcklwd             m6,                 m4,                  m5
+    pmaddwd               m6,                 [r5 + mmsize]
+    paddd                 m0,                 m6
+    punpckhwd             m4,                 m5
+    pmaddwd               m4,                 [r5 + mmsize]
+    paddd                 m1,                 m4
+
+    movu                  m4,                 [r0 + 2 * r1]
+    punpcklwd             m6,                 m5,                  m4
+    pmaddwd               m6,                 [r5 + mmsize]
+    paddd                 m2,                 m6
+    punpckhwd             m5,                 m4
+    pmaddwd               m5,                 [r5 + mmsize]
+    paddd                 m3,                 m5
+
+    paddd                 m0,                 m7
+    paddd                 m1,                 m7
+    paddd                 m2,                 m7
+    paddd                 m3,                 m7
+    psrad                 m0,                 INTERP_SHIFT_PS
+    psrad                 m1,                 INTERP_SHIFT_PS
+    psrad                 m2,                 INTERP_SHIFT_PS
+    psrad                 m3,                 INTERP_SHIFT_PS
+
+    packssdw              m0,                 m1
+    packssdw              m2,                 m3
+    movu                  [r2],               m0
+    movu                  [r2 + r3],          m2
+%endmacro
+
+;-----------------------------------------------------------------------------------------------------------------
+; void interp_4tap_vert(int16_t *src, intptr_t srcStride, int16_t *dst, 
intptr_t dstStride, int coeffIdx)
+;-----------------------------------------------------------------------------------------------------------------
+%macro FILTER_VER_PS_CHROMA_32xN_AVX512 1
+INIT_ZMM avx512
+cglobal interp_4tap_vert_ps_32x%1, 5, 7, 9
+    add                   r1d,                r1d
+    add                   r3d,                r3d
+    sub                   r0,                 r1
+    shl                   r4d,                7
+
+%ifdef PIC
+    lea                   r5,                 [tab_ChromaCoeffV_avx512]
+    lea                   r5,                 [r5 + r4]
+%else
+    lea                   r5,                 [tab_ChromaCoeffV_avx512 + r4]
+%endif
+    vbroadcasti32x4       m7,                 [INTERP_OFFSET_PS]
+
+%rep %1/2 - 1
+    PROCESS_CHROMA_VERT_PS_32x2_AVX512
+    lea                   r2,                 [r2 + 2 * r3]
+%endrep
+    PROCESS_CHROMA_VERT_PS_32x2_AVX512
+    RET
+%endmacro
+
+%if ARCH_X86_64
+FILTER_VER_PS_CHROMA_32xN_AVX512 8
+FILTER_VER_PS_CHROMA_32xN_AVX512 16
+FILTER_VER_PS_CHROMA_32xN_AVX512 24
+FILTER_VER_PS_CHROMA_32xN_AVX512 32
+FILTER_VER_PS_CHROMA_32xN_AVX512 48
+FILTER_VER_PS_CHROMA_32xN_AVX512 64
+%endif
 
;-------------------------------------------------------------------------------------------------------------
 ;ipfilter_chroma_avx512 code end
 
;-------------------------------------------------------------------------------------------------------------
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