# HG changeset patch
# User Vignesh Vijayakumar<vign...@multicorewareinc.com>
# Date 1511503473 -19800
#      Fri Nov 24 11:34:33 2017 +0530
# Node ID ecaf36f641dd1428d556f172e83cf7078f0287fb
# Parent  49850b347ef45834d15586c870c898a021001644
x86: AVX512 interp_8tap_vert_sp_8xN and interp_8tap_vert_ss_8xN

luma_vss
Size  |  AVX2 performance | AVX512 performance
----------------------------------------------
8x8   |      7.52x        |      12.03x
8x16  |      10.54x       |      12.68x
8x32  |      10.37x       |      12.93x

luma_vsp
Size  |  AVX2 performance | AVX512 performance
----------------------------------------------
8x8   |      11.01x       |      12.99x
8x16  |      12.10x       |      14.50x
8x32  |      12.86x       |      14.72x

diff -r 49850b347ef4 -r ecaf36f641dd source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp      Fri Nov 24 10:36:36 2017 +0530
+++ b/source/common/x86/asm-primitives.cpp      Fri Nov 24 11:34:33 2017 +0530
@@ -2835,6 +2835,9 @@
         p.chroma[X265_CSP_I422].pu[CHROMA_422_24x64].filter_vsp = 
PFX(interp_4tap_vert_sp_24x64_avx512);
         p.chroma[X265_CSP_I444].pu[LUMA_24x32].filter_vsp = 
PFX(interp_4tap_vert_sp_24x32_avx512);
 
+        p.pu[LUMA_8x8].luma_vss = PFX(interp_8tap_vert_ss_8x8_avx512);
+        p.pu[LUMA_8x16].luma_vss = PFX(interp_8tap_vert_ss_8x16_avx512);
+        p.pu[LUMA_8x32].luma_vss = PFX(interp_8tap_vert_ss_8x32_avx512);
         p.pu[LUMA_16x4].luma_vss = PFX(interp_8tap_vert_ss_16x4_avx512);
         p.pu[LUMA_16x8].luma_vss = PFX(interp_8tap_vert_ss_16x8_avx512);
         p.pu[LUMA_16x12].luma_vss = PFX(interp_8tap_vert_ss_16x12_avx512);
@@ -2852,6 +2855,9 @@
         p.pu[LUMA_64x64].luma_vss = PFX(interp_8tap_vert_ss_64x64_avx512);
         p.pu[LUMA_48x64].luma_vss = PFX(interp_8tap_vert_ss_48x64_avx512);
 
+        p.pu[LUMA_8x8].luma_vsp = PFX(interp_8tap_vert_sp_8x8_avx512);
+        p.pu[LUMA_8x16].luma_vsp = PFX(interp_8tap_vert_sp_8x16_avx512);
+        p.pu[LUMA_8x32].luma_vsp = PFX(interp_8tap_vert_sp_8x32_avx512);
         p.pu[LUMA_16x4].luma_vsp = PFX(interp_8tap_vert_sp_16x4_avx512);
         p.pu[LUMA_16x8].luma_vsp = PFX(interp_8tap_vert_sp_16x8_avx512);
         p.pu[LUMA_16x12].luma_vsp = PFX(interp_8tap_vert_sp_16x12_avx512);
diff -r 49850b347ef4 -r ecaf36f641dd source/common/x86/ipfilter16.asm
--- a/source/common/x86/ipfilter16.asm  Fri Nov 24 10:36:36 2017 +0530
+++ b/source/common/x86/ipfilter16.asm  Fri Nov 24 11:34:33 2017 +0530
@@ -10795,6 +10795,185 @@
 
;-------------------------------------------------------------------------------------------------------------
 ;avx512 luma_vss and luma_vsp code start
 
;-------------------------------------------------------------------------------------------------------------
+%macro PROCESS_LUMA_VERT_S_8x8_AVX512 1
+    lea                  r6,                  [r0 + 4 * r1]
+    movu                 xm1,                 [r0]                           
;0 row
+    vinserti32x4         m1,                  [r0 + 2 * r1],          1
+    vinserti32x4         m1,                  [r0 + 4 * r1],          2
+    vinserti32x4         m1,                  [r6 + 2 * r1],          3
+    movu                 xm3,                 [r0 + r1]                      
;1 row
+    vinserti32x4         m3,                  [r0 + r7],              1
+    vinserti32x4         m3,                  [r6 + r1],              2
+    vinserti32x4         m3,                  [r6 + r7],              3
+    punpcklwd            m0,                  m1,                     m3
+    pmaddwd              m0,                  m15
+    punpckhwd            m1,                  m3
+    pmaddwd              m1,                  m15
+
+    movu                 xm4,                 [r0 + 2 * r1]                  
;2 row
+    vinserti32x4         m4,                  [r0 + 4 * r1],          1
+    vinserti32x4         m4,                  [r6 + 2 * r1],          2
+    vinserti32x4         m4,                  [r6 + 4 * r1],          3
+    punpcklwd            m2,                  m3,                     m4
+    pmaddwd              m2,                  m15
+    punpckhwd            m3,                  m4
+    pmaddwd              m3,                  m15
+
+    lea                  r4,                  [r6 + 4 * r1]
+    movu                 xm5,                 [r0 + r7]                      
;3 row
+    vinserti32x4         m5,                  [r6 + r1],              1
+    vinserti32x4         m5,                  [r6 + r7],              2
+    vinserti32x4         m5,                  [r4 + r1],              3
+    punpcklwd            m6,                  m4,                     m5
+    pmaddwd              m6,                  m16
+    punpckhwd            m4,                  m5
+    pmaddwd              m4,                  m16
+
+    paddd                m0,                  m6
+    paddd                m1,                  m4
+
+    movu                 xm4,                 [r0 + 4 * r1]                  
;4 row
+    vinserti32x4         m4,                  [r6 + 2 * r1],              1
+    vinserti32x4         m4,                  [r6 + 4 * r1],              2
+    vinserti32x4         m4,                  [r4 + 2 * r1],              3
+    punpcklwd            m6,                  m5,                     m4
+    pmaddwd              m6,                  m16
+    punpckhwd            m5,                  m4
+    pmaddwd              m5,                  m16
+
+    paddd                m2,                  m6
+    paddd                m3,                  m5
+
+    movu                 xm11,                [r6 + r1]                      
;5 row
+    vinserti32x4         m11,                 [r6 + r7],              1
+    vinserti32x4         m11,                 [r4 + r1],              2
+    vinserti32x4         m11,                 [r4 + r7],              3
+    punpcklwd            m8,                  m4,                     m11
+    pmaddwd              m8,                  m17
+    punpckhwd            m4,                  m11
+    pmaddwd              m4,                  m17
+
+    movu                 xm12,                [r6 + 2 * r1]                  
;6 row
+    vinserti32x4         m12,                 [r6 + 4 * r1],          1
+    vinserti32x4         m12,                 [r4 + 2 * r1],          2
+    vinserti32x4         m12,                 [r4 + 4 * r1],          3
+    punpcklwd            m10,                 m11,                    m12
+    pmaddwd              m10,                 m17
+    punpckhwd            m11,                 m12
+    pmaddwd              m11,                 m17
+
+    lea                  r8,                  [r4 + 4 * r1]
+    movu                 xm13,                [r6 + r7]                      
;7 row
+    vinserti32x4         m13,                 [r4 + r1],              1
+    vinserti32x4         m13,                 [r4 + r7],              2
+    vinserti32x4         m13,                 [r8 + r1],              3
+    punpcklwd            m14,                 m12,                    m13
+    pmaddwd              m14,                 m18
+    punpckhwd            m12,                 m13
+    pmaddwd              m12,                 m18
+
+    paddd                m8,                  m14
+    paddd                m4,                  m12
+    paddd                m0,                  m8
+    paddd                m1,                  m4
+
+    movu                 xm12,                [r6 + 4 * r1]                 ; 
8 row
+    vinserti32x4         m12,                 [r4 + 2 * r1],          1
+    vinserti32x4         m12,                 [r4 + 4 * r1],          2
+    vinserti32x4         m12,                 [r8 + 2 * r1],          3
+    punpcklwd            m14,                 m13,                    m12
+    pmaddwd              m14,                 m18
+    punpckhwd            m13,                 m12
+    pmaddwd              m13,                 m18
+
+    paddd                m10,                 m14
+    paddd                m11,                 m13
+    paddd                m2,                  m10
+    paddd                m3,                  m11
+
+%ifidn %1, sp
+    paddd                m0,                  m19
+    paddd                m1,                  m19
+    paddd                m2,                  m19
+    paddd                m3,                  m19
+
+    psrad                m0,                  INTERP_SHIFT_SP
+    psrad                m1,                  INTERP_SHIFT_SP
+    psrad                m2,                  INTERP_SHIFT_SP
+    psrad                m3,                  INTERP_SHIFT_SP
+
+    packssdw             m0,                  m1
+    packssdw             m2,                  m3
+    CLIPW2               m0,                  m2,                   m20,       
          m21
+%else
+    psrad                m0,                  6
+    psrad                m1,                  6
+    psrad                m2,                  6
+    psrad                m3,                  6
+
+    packssdw             m0,                  m1
+    packssdw             m2,                  m3
+%endif
+
+    movu                 [r2],                xm0
+    movu                 [r2 + r3],           xm2
+    vextracti32x4        [r2 + 2 * r3],       m0,                  1
+    vextracti32x4        [r2 + r5],           m2,                  1
+    lea                  r2,                  [r2 + 4 * r3]
+    vextracti32x4        [r2],                m0,                  2
+    vextracti32x4        [r2 + r3],           m2,                  2
+    vextracti32x4        [r2 + 2 * r3],       m0,                  3
+    vextracti32x4        [r2 + r5],           m2,                  3
+%endmacro
+;-----------------------------------------------------------------------------------------------------------------
+; void interp_8tap_vert(int16_t *src, intptr_t srcStride, int16_t *dst, 
intptr_t dstStride, int coeffIdx)
+;-----------------------------------------------------------------------------------------------------------------
+%macro FILTER_VER_S_LUMA_8xN_AVX512 2
+INIT_ZMM avx512
+cglobal interp_8tap_vert_%1_8x%2, 5, 9, 22
+    add                   r1d,                r1d
+    add                   r3d,                r3d
+    lea                   r7,                 [3 * r1]
+    sub                   r0,                 r7
+    shl                   r4d,                8
+%ifdef PIC
+    lea                   r5,                 [tab_LumaCoeffVer_avx512]
+    mova                  m15,                [r5 + r4]
+    mova                  m16,                [r5 + r4 + 1 * mmsize]
+    mova                  m17,                [r5 + r4 + 2 * mmsize]
+    mova                  m18,                [r5 + r4 + 3 * mmsize]
+%else
+    lea                   r5,                 [tab_LumaCoeffVer_avx512 + r4]
+    mova                  m15,                [r5]
+    mova                  m16,                [r5 + 1 * mmsize]
+    mova                  m17,                [r5 + 2 * mmsize]
+    mova                  m18,                [r5 + 3 * mmsize]
+%endif
+%ifidn %1, sp
+    vbroadcasti32x4       m19,                [INTERP_OFFSET_SP]
+    pxor                  m20,                m20
+    vbroadcasti32x8       m21,                [pw_pixel_max]
+%endif
+    lea                   r5,                 [3 * r3]
+
+%rep %2/8 - 1
+    PROCESS_LUMA_VERT_S_8x8_AVX512 %1
+    lea                   r0,                 [r4]
+    lea                   r2,                 [r2 + 4 * r3]
+%endrep
+    PROCESS_LUMA_VERT_S_8x8_AVX512 %1
+    RET
+%endmacro
+
+%if ARCH_X86_64
+    FILTER_VER_S_LUMA_8xN_AVX512 ss, 8
+    FILTER_VER_S_LUMA_8xN_AVX512 ss, 16
+    FILTER_VER_S_LUMA_8xN_AVX512 ss, 32
+    FILTER_VER_S_LUMA_8xN_AVX512 sp, 8
+    FILTER_VER_S_LUMA_8xN_AVX512 sp, 16
+    FILTER_VER_S_LUMA_8xN_AVX512 sp, 32
+%endif
+
 %macro PROCESS_LUMA_VERT_S_16x4_AVX512 1
     movu                 ym1,                 [r0]
     movu                 ym3,                 [r0 + r1]
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