Hello,
I'm getting a segfault writing a PCB netlist for a schematic with
hierarchy.
subcircuit.ps is a schematic with symbol.
toplevel1.ps is a schematic containing 1 instance of subcircuit.
toplevel2.ps is a schematic containing 2 instances of subcircuit.
================================================================================
"Write pcb" of toplevel1.ps without loading dependecies works as expected.
int1 X1-ingnd J2-1
int2 X1-out J4-2
vee J1-4 C1-2
vcc J1-1 C2-1
gnd J4-1 J1-2 J1-3 C2-2 C1-1
int7 X1-inp J2-3
int8 X1-inm J2-2
================================================================================
"Write pcb" of toplevel1.ps with loading dependecies works as expected.
NET1 X1/R1-1 X1/C5-2 X1/C6-1 X1/C4-1
NET2 X1/D4-2 X1/D5-2 X1/D6-2
NET3 X1/D2-1 X1/D3-1 X1/D1-1
NET4 X1/U1-2 X1/R2-2 X1/C5-1 X1/D2-2 X1/D4-1
NET5 X1/U1-3 X1/R3-2 X1/C6-2 X1/D3-2 X1/D5-1
NET6 X1/U1-5 X1/R1-2 X1/C3-2
NET7 X1/U1-8 X1/C3-1
int2 X1/U1-6 J4-2
vee X1/U1-4 X1/C2-2 X1/D6-1 J1-4 C1-2
vcc X1/U1-7 X1/C1-1 X1/D1-2 J1-1 C2-1
gnd X1/U1-1 X1/C4-2 X1/C1-2 X1/C2-1 J2-1 J4-1 J1-2 \
J1-3 C2-2 C1-1
int7 X1/R3-1 J2-3
int8 X1/R2-1 J2-2
================================================================================
"Write pcb" of toplevel2.ps without loading dependecies works as expected.
int1 X1-ingnd J2-1
int2 X1-out J4-2
vee J1-4 C1-2
vcc J1-1 C2-1
int7 X1-inp J2-3
int8 X1-inm J2-2
int9 X2-ingnd J3-1
int10 X2-out J5-2
gnd J4-1 J1-2 J1-3 C2-2 C1-1 J5-1
int12 X2-inp J3-3
int13 X2-inm J3-2
================================================================================
"Write pcb" of toplevel2.ps with loading dependecies segfaults.
================================================================================
Is this a supported operation?
To get this far, I had to add "pcb:X?" info labels to the subcircuit
symbol. Otherwise, toplevel2.ps without loading dependencies would also
segfault. Maybe I'm still missing something?
-- Daniel
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