On 10/27/2017 01:49 PM, Juergen Gross wrote: > Physical addresses on processors supporting 5 level paging can be up to > 52 bits wide. For a Xen pv guest running on such a machine those > physical addresses have to be supported in order to be able to use any > memory on the machine even if the guest itself does not support 5 level > paging. > > So when reading/writing a MFN from/to a pte don't use the kernel's > PTE_PFN_MASK but a new XEN_PTE_MFN_MASK allowing full 40 bit wide MFNs. > > Signed-off-by: Juergen Gross <jgr...@suse.com>
Applied to for-linus-4.15 -boris _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org https://lists.xen.org/xen-devel
