On Tue, 27 Jan 2015, 신정섭 wrote: > > Hi > > I'm studying about Xen 4.4.0 and Xen 4.5.0 on ARM > > > > I have some questions about Interrupt and event channel on ARM. > > > > 1. > In Xen 4.4.X and Xen 4.5.0 (GIC v2), all pirq(physical irq) are go to pcpu0 > (physical cpu). After pirq, Xen run in pcpu0 only > inject virq(virtual irq) to vcpu0 of Dom0. > I think injection of virtual irq to proper vcpu carry out interrupt load > balancing and reducing interrupt latency. > Why dose Xen only route virtual to vcpu0 of Dom0? For only simple?? Actually Xen 4.5 is capable of routing irqs to any phsical and virtual cpus.
> 2. > Xen 4.5.0 support GiC v3. I saw code about GICv3 in Xen 4.5.0. > > it seems that GICv3 add some virq interrupt routing interface such as > 'GICD_IROUTER_SPI_MODE_ANY' > > and support irq migration. But i know that 'GICv3 Architecture Specification' > release specification in later this year. > How can Xen 4.5.0 Developers get GICv3 Information and where can i get GICv3 > Information?? The specification is already available to partners. > 3. > > In Xen 4.4.0, Xen occur 'GIC_SGI_EVENT_CHECK' sgi interrupt to check event > channel. After GIC_SGI_EVENT_CHECK sgi, > 'leave_hypervisor_tail' function is executed on return path. > > leave_hypervisor_tail function inject virq of event channel. > > But In Xen 4.5.0, After GIC_SGI_EVENT_CHECK sgi, leave_hypervisor_tail > dosen't inject virq of event channel. > > and There is no virq injection of event channel on return path. > > So I think, to send GIC_SGI_EVENT_CHECK sgi is meaning less in Xen 4.5.0. It interrups the execution of another vcpu and makes sure that the Xen entry code is executed, including enter_hypervisor_head that calls gic_clear_lrs. > Right?? Am i wrong? > > > > > > Thanks > > [?img=m%2FRm%2BBFm%2BBFShAnZFAM9M6MlK4tZM6EZaxvqMoKdaxF4aAiSpAC0FzUZF4KdMvIo%2BrkSKAb5W4d5W4C5bX0q%2BzkR74FTWx%2FsDzk57630%2B4knt > zwGbX3q7NC0WSlTb4b%3D.gif] >
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