>>> On 16.03.17 at 17:31, <andrew.coop...@citrix.com> wrote:
> Some bits are unconditionally reserved in pagetable entries, or reserved
> because of alignment restrictions. Other bits are reserved because of control
> register configuration.
> Introduce helpers which take an individual vcpu and guest pagetable entry, and
> calculates whether any reserved bits are set.
> While here, add a couple of newlines to aid readability.
> Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com>
Reviewed-by: Jan Beulich <jbeul...@suse.com>
with the same remarks as on the prior patch for ...
> @@ -182,6 +216,21 @@ static inline bool guest_supports_l2_superpages(const
> struct vcpu *v)
> || (v->arch.hvm_vcpu.guest_cr & X86_CR4_PSE)));
> +static inline bool guest_supports_pse36(const struct domain *d)
> + /*
> + * Only called in the context of 2-level guests, after
> + * guest_supports_l2_superpages() has indicated true.
> + *
> + * Once L2 superpages are active, here are no control register settings
> + * for the hardware pagewalk on the subject of PSE36. If the guest
> + * constructs a PSE36 superpage on capable hardware, it will function
> + * irrespective of whether the feature is advertised. Xen's model of
> + * performing a pagewalk should match.
> + */
> + return paging_mode_hap(d) && cpu_has_pse36;
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