Hi Julien,
On 11 May 2017 at 13:07, Julien Grall <julien.gr...@arm.com> wrote: > Looking again at the documentation and chatting with other ARM folks. I was > wrong on some part, sorry for the confusion. Thank you for this investigation. One can't fit whole ARMv8 TRM in one's head :) > It turns out that if you don't need to flush the TLBs when disabling the > HCR_EL2.VM (this is what Linux does for KVM). So disabling stage-2 for EL0 > app would be ok. Aha, these are good news. > But you still need to allocate a VMID per EL0 app as TLBs will still depend > on it even with stage-2 disabled. I see. But I will need to allocate VMID in any case, right? > Even if we keep stage-2 enabled, we would have to create dummly page tables > of stage-1 because the memory attribute would impact performance and at > least not allow the EL0 app to move (see D4.2.8 in ARM DDI > 0487A.k_iss10775). In this case, 1:1 page tables with a block map (e.g 1GB) > would be sufficient and rely on stage-2 page tables. Yes, I did exactly this in my PoC. I'm was curious on disabling stage-2 because I don't want to mess with p2m context save/restore functions. Good to know that it is possible. > Lastly, can you remind me with platform you are using for testing? It is Renesas Rcar Gen3. It is Big-Little platform, but currently we use only four A57 cores. -- WBR Volodymyr Babchuk aka lorc [+380976646013] mailto: vlad.babc...@gmail.com _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org https://lists.xen.org/xen-devel
