Hi Volodymyr,

On 09/08/2017 20:44, Volodymyr Babchuk wrote:
Name "iss" in this case was used not exactly correctly, because this
is only part of HSR.ISS field. ARM refence manual denotes this
part of ISS as RES0 when it describes encoding for conditional
exceptions (ARM DDI 0487A.k pages D7-1939 - D7-1949).   

Please use the latest ARM manual (i.e ARM DDI 0487A.b). And this is still not true. If you look at:
        - WFI/WFE, bit 1 is not res0.
        - MCR/MRC, all bits are defined

If you really want to rename this field, then name it pad or ign. But res0 is completely bogus.


Signed-off-by: Volodymyr Babchuk <volodymyr_babc...@epam.com>

- Added reference to ARM archtecture manual in the commit message.

 xen/include/asm-arm/processor.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 855ded1..f640d54 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -434,7 +434,7 @@ union hsr {

     /* Common to all conditional exception classes (0x0N, except 0x00). */
     struct hsr_cond {
-        unsigned long iss:20;  /* Instruction Specific Syndrome */
+        unsigned long res0:20;  /* Reserved */
         unsigned long cc:4;    /* Condition Code */
         unsigned long ccvalid:1;/* CC Valid */
         unsigned long len:1;   /* Instruction length */

Julien Grall

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