On Mon, Sep 11, 2017 at 02:00:48PM +0800, Haozhong Zhang wrote:
> The 64-bit DMAR fault address is composed of two 32 bits registers
> DMAR_FEADDR_REG and DMAR_FEUADDR_REG. According to VT-d spec:
> "Software is expected to access 32-bit registers as aligned doublewords",
> a hypervisor should use two 32-bit writes to DMAR_FEADDR_REG and
> DMAR_FEUADDR_REG separately in order to update a 64-bit fault address,
> rather than a 64-bit write to DMAR_FEADDR_REG.
I would add:
"Note that when x2APIC is disabled DMAR_FEUADDR_REG is reserved and it's not
necessary to update it."
> Though I haven't seen any errors caused by such one 64-bit write on
> real machines, it's still better to follow the specification.
> Signed-off-by: Haozhong Zhang <haozhong.zh...@intel.com>
Given the reply from Kevin:
Reviewed-by: Roger Pau Monné <roger....@citrix.com>
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