We do not set HCR_EL2.TSW so we will never see these.
This is undoubtedly wrong, but for now remove the dead code.
However, retain the HSR_SYSREG_* added by the precursor to this patch,
although they aren't used they are factually accurate and may as well
be kept for future use.
Signed-off-by: Ian Campbell <ian.campb...@citrix.com>
---
v5: Replaced "xen: arm: don't pretend to handle cache maintenance by
set/way"
v4: New patch
---
xen/arch/arm/traps.c | 13 -------------
xen/include/asm-arm/sysregs.h | 4 ++++
2 files changed, 4 insertions(+), 13 deletions(-)
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 22beab7..d296f50 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -1564,19 +1564,6 @@ static void do_cp15_32(struct cpu_user_regs *regs,
switch ( hsr.bits & HSR_CP32_REGS_MASK )
{
- case HSR_CPREG32(DCCISW):
- if ( cp32.read )
- {
- dprintk(XENLOG_ERR,
- "attempt to read from write-only register DCCISW\n");
- domain_crash_synchronous();
- }
-#ifdef CONFIG_ARM_32
- WRITE_CP32(*r, DCCISW);
-#else
- asm volatile("dc cisw, %0;" : : "r" (*r) : "memory");
-#endif
- break;
case HSR_CPREG32(CNTP_CTL):
case HSR_CPREG32(CNTP_TVAL):
if ( !vtimer_emulate(regs, hsr) )
diff --git a/xen/include/asm-arm/sysregs.h b/xen/include/asm-arm/sysregs.h
index df8e070..2e256cc 100644
--- a/xen/include/asm-arm/sysregs.h
+++ b/xen/include/asm-arm/sysregs.h
@@ -40,6 +40,10 @@
((__HSR_SYSREG_##crm) << HSR_SYSREG_CRM_SHIFT) | \
((__HSR_SYSREG_##op2) << HSR_SYSREG_OP2_SHIFT)
+#define HSR_SYSREG_DCISW HSR_SYSREG(1,0,c7,c6,2)
+#define HSR_SYSREG_DCCSW HSR_SYSREG(1,0,c7,c10,2)
+#define HSR_SYSREG_DCCISW HSR_SYSREG(1,0,c7,c14,2)
+
#define HSR_SYSREG_MDSCR_EL1 HSR_SYSREG(2,0,c0,c2,2)
#define HSR_SYSREG_OSLAR_EL1 HSR_SYSREG(2,0,c1,c0,4)
#define HSR_SYSREG_OSDLR_EL1 HSR_SYSREG(2,0,c1,c3,4)
--
1.7.10.4
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