On Mon, 2015-06-01 at 20:56 +0800, Chen Baozi wrote: > From: Chen Baozi <baoz...@gmail.com> > > According to ARM CPUs bindings, the reg field should match the MPIDR's > affinity bits. We will use AFF0 and AFF1 when constructing the reg value > of the guest at the moment, for it is enough for the current max vcpu > number. > > Signed-off-by: Chen Baozi <baoz...@gmail.com> > Reviewed-by: Julien Grall <julien.gr...@citrix.com>
Acked-by: Ian Campbell <ian.campb...@citrix.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel
