>>> On 08.08.16 at 15:41, <boris.ostrov...@oracle.com> wrote: > While AMD APM suggests that reserved MSR bits are not supposed to be > touched, it is not clear how (or whether) HW enforces this for PMU > registers. At least on some family 10h processors writes of these bits > are apparently ignored: guests (such as Linux) assume that the bits > are zero and write the MSRs with that assumption in mind even though > the bits are set by the time OS/hypervisor starts runnning.
So how did these bits become non-zero then? Independent of that I think the relaxation would better only be done for those older CPUs. Jan _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org https://lists.xen.org/xen-devel
