On 24/10/16 13:17, Jan Beulich wrote: > Suggested-by: Andrew Cooper <andrew.coop...@citrix.com> > Signed-off-by: Jan Beulich <jbeul...@suse.com>
Reviewed-by: Andrew Cooper <andrew.coop...@citrix.com> > > --- a/xen/tools/gen-cpuid.py > +++ b/xen/tools/gen-cpuid.py > @@ -196,8 +196,9 @@ def crunch_numbers(state): > > # SSE is taken to mean support for the %XMM registers as well as the > # instructions. Several futher instruction sets are built on core > - # %XMM support, without specific inter-dependencies. > - SSE: [SSE2, SSE3, SSSE3, SSE4A, > + # %XMM support, without specific inter-dependencies. Additionally > + # AMD has a special mis-alignment sub-mode. > + SSE: [SSE2, SSE3, SSSE3, SSE4A, MISALIGNSSE, > AESNI, SHA], > > # SSE2 was re-specified as core instructions for 64bit. > > > _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org https://lists.xen.org/xen-devel
