>>> On 27.02.17 at 15:03, <andrew.coop...@citrix.com> wrote: > Outstanding hardware issues discovered include: > 1) There is an observable delay in AMD Fam 10h processors between loading a > segment selector, and the results of the LDT/GDT memory access being > visible in the pagetables (via the Access bits being set).
Are you saying the processor continues executing instructions while the accessed bits are still clear? Or just that it takes very long to complete the instruction doing the descriptor table access? Jan _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org https://lists.xen.org/xen-devel
