>>> On 28.02.18 at 16:37, <roger....@citrix.com> wrote:
> On Fri, Feb 23, 2018 at 07:07:18PM +0000, Wei Liu wrote:
>> On Fri, Feb 23, 2018 at 01:27:43PM +0000, Roger Pau Monne wrote:
>> > --- a/arch/x86/include/arch/lib.h
>> > +++ b/arch/x86/include/arch/lib.h
>> > @@ -392,6 +392,20 @@ static inline void write_xcr0(uint64_t xcr0)
>> > xsetbv(0, xcr0);
>> > }
>> >
>> > +static inline uint64_t rdtsc(void)
>> > +{
>> > + uint32_t low, high;
>> > +
>> > + asm volatile ("rdtsc" : "=a" (low), "=d" (high));
>> > +
>>
>> You probably need to add lfence or mfence. See rdtsc_ordered in Xen.
>
> Oh, OK that's news to me. I guess just using a lfence before it
> should be fine.
Except that on AMD, without LFENCE made dispatch serializing,
you'd need MFENCE.
Jan
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