Hi Andre,

On 05/03/18 16:03, Andre Przywara wrote:
The new VGIC will shortly use more bits of the various GIC registers, so
add the respective definitions from the manual.
This series does not seem to use any of the new value you added. Did I miss anything?

Note that I am not against this patch, but the commit message should be updated.

This includes bits from the GICC_CTL register and some minor other bits.

s/GICC_CTL/GICC_CLTR/ and same with the update you do below as there are only limited use in the code. So should not much impact the rest of the series.

Adjust the usage of ICC_CTL_ENABLE on the way, to be more precise about

Did you mean GICC_CTLR_ENABLE?

which of the two enable bits we actually deal with.

Signed-off-by: Andre Przywara <andre.przyw...@linaro.org>
---
Changelog RFC ... v1:
- extend commit message

  xen/arch/arm/gic-v2.c     |  2 +-
  xen/include/asm-arm/gic.h | 18 ++++++++++++++++--
  2 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
index 2b271ba322..7938a42591 100644
--- a/xen/arch/arm/gic-v2.c
+++ b/xen/arch/arm/gic-v2.c
@@ -358,7 +358,7 @@ static void gicv2_cpu_init(void)
      /* Finest granularity of priority */
      writel_gicc(0x0, GICC_BPR);
      /* Turn on delivery */
-    writel_gicc(GICC_CTL_ENABLE|GICC_CTL_EOI, GICC_CTLR);
+    writel_gicc(GICC_CTL_ENABLE0|GICC_CTL_EOI, GICC_CTLR);
  }
static void gicv2_cpu_disable(void)
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index b3f840ea9a..8fab458d7f 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -77,6 +77,7 @@
  #define GICC_EOIR       (0x0010)
  #define GICC_RPR        (0x0014)
  #define GICC_HPPIR      (0x0018)
+#define GICC_ABPR       (0x001c)
  #define GICC_APR        (0x00D0)
  #define GICC_NSAPR      (0x00E0)
  #define GICC_IIDR       (0x00FC)
@@ -102,8 +103,18 @@
  #define GICD_TYPE_SEC   0x400
  #define GICD_TYPER_DVIS (1U << 18)
-#define GICC_CTL_ENABLE 0x1
-#define GICC_CTL_EOI    (0x1 << 9)
+#define GICC_CTL_ENABLE0_SHIFT  0
+#define GICC_CTL_ENABLE0        (1U << GICC_CTL_ENABLE0_SHIFT)
+#define GICC_CTL_ENABLE1_SHIFT  1
+#define GICC_CTL_ENABLE1        (1U << GICC_CTL_ENABLE1)
+#define GICC_CTL_AC_SHIFT       2
+#define GICC_CTL_AC             (1U << GICC_CTL_AC_SHIFT)
+#define GICC_CTL_FIQEN_SHIFT    3
+#define GICC_CTL_FIQEN          (1U << GICC_CTL_FIQEN_SHIFT)
+#define GICC_CTL_CBPR_SHIFT     4
+#define GICC_CTL_CBPR           (1U << GICC_CTL_CBPR_SHIFT)
+#define GICC_CTL_EOI_SHIFT      9
+#define GICC_CTL_EOI            (1U << GICC_CTL_EOI_SHIFT)
#define GICC_IA_IRQ 0x03ff
  #define GICC_IA_CPU_MASK  0x1c00
@@ -127,6 +138,9 @@
  #define GICH_MISR_VGRP1E  (1 << 6)
  #define GICH_MISR_VGRP1D  (1 << 7)
+#define GICV_PMR_PRIORITY_SHIFT 3
+#define GICV_PMR_PRIORITY_MASK         (0x1f << GICV_PMR_PRIORITY_SHIFT)
+
  /*
   * The minimum GICC_BPR is required to be in the range 0-3. We set
   * GICC_BPR to 0 but we must expect that it might be 3. This means we


Cheers,

--
Julien Grall

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