From: David E. Box <david.e....@linux.intel.com>
Gemini Lake uses the same C-states as Broxton and also uses the
IRTL MSR's to determine maximum C-state latency.
Signed-off-by: David E. Box <david.e....@linux.intel.com>
Acked-by: Len Brown <len.br...@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wyso...@intel.com>
[Linux commit 1b2e87687d3f951a66900cab6f1583d94099d2f7]
Signed-off-by: Jan Beulich <jbeul...@suse.com>
--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -957,6 +957,7 @@ static const struct x86_cpu_id intel_idl
ICPU(0x57, knl),
ICPU(0x85, knl),
ICPU(0x5c, bxt),
+ ICPU(0x7a, bxt),
ICPU(0x5f, dnv),
{}
};
@@ -1102,6 +1103,7 @@ static void __init mwait_idle_state_tabl
ivt_idle_state_table_update();
break;
case 0x5c: /* BXT */
+ case 0x7a:
bxt_idle_state_table_update();
break;
case 0x5e: /* SKL-H */
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