Hi,
On 12/03/18 12:42, mja...@caviumnetworks.com wrote:
From: Manish Jaggi <manish.ja...@cavium.com>
Add MIDR values for Cavium ThunderX1 SoC's (88xx, 81xx, 83xx).
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
---
xen/include/asm-arm/processor.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 65eb1071e1..649a3ae3ca 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -43,15 +43,24 @@
})
#define ARM_CPU_IMP_ARM 0x41
+#define ARM_CPU_IMP_CAVIUM 0x43
#define ARM_CPU_PART_CORTEX_A15 0xC0F
#define ARM_CPU_PART_CORTEX_A53 0xD03
#define ARM_CPU_PART_CORTEX_A57 0xD07
+#define CAVIUM_CPU_PART_THUNDERX 0x0A1
In the commit message you say you add MIDR for 88xx but I don't see it.
I suppose this is this one. If so, please rename it accordingly.
+#define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
+#define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3
Can you please try to at least align between themselves the things to
you add?
+
#define MIDR_CORTEX_A15 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM,
ARM_CPU_PART_CORTEX_A15)
#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM,
ARM_CPU_PART_CORTEX_A53)
#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM,
ARM_CPU_PART_CORTEX_A57)
+#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
+#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM,
CAVIUM_CPU_PART_THUNDERX_81XX)
+#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM,
CAVIUM_CPU_PART_THUNDERX_83XX)
+
/* MPIDR Multiprocessor Affinity Register */
#define _MPIDR_UP (30)
#define MPIDR_UP (_AC(1,U) << _MPIDR_UP)
Cheers,
--
Julien Grall
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