Hi Manish,
On 03/16/2018 11:58 AM, Manish Jaggi wrote:
This patch is ported to xen from linux commit
d70c7b31a60f2458f35c226131f2a01a7a98b6cf
Add a handler for reading/writing the guest's view of the ICC_BPR1_EL1
register, which is located in the ICH_VMCR_EL2.BPR1 field.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
As you port commit by commit, please at least mention Marc as he is the
original author of that patch.
diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
index 56b02fd45b..364785d3ac 100644
--- a/xen/arch/arm/arm64/vgic-v3-sr.c
+++ b/xen/arch/arm/arm64/vgic-v3-sr.c
@@ -20,10 +20,76 @@
#include <asm/regs.h>
#include <asm/traps.h>
#include <asm/system.h>
+#include <asm/gic_v3_defs.h>
+
+#define vtr_to_nr_pre_bits(v) ((((uint32_t)(v) >> 26) & 7) + 1)
+
+static int __vgic_v3_bpr_min(void)
Please remove one of the space.
As you convert to Xen coding style, please remove __ from all function
names.
+{
+ /* See Pseudocode for VPriorityGroup */
+ return 8 - vtr_to_nr_pre_bits(READ_SYSREG32(ICH_VTR_EL2));
+}
+
+static unsigned int __vgic_v3_get_bpr0(uint32_t vmcr)
+{
+ return (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
+}
+
+static unsigned int __vgic_v3_get_bpr1(uint32_t vmcr)
+{
+ unsigned int bpr;
+
+ if ( vmcr & ICH_VMCR_CBPR_MASK )
+ {
+ bpr = __vgic_v3_get_bpr0(vmcr);
+ if ( bpr < 7 )
+ bpr++;
+ }
+ else
+ bpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
+
+ return bpr;
+}
+
+static void __vgic_v3_read_bpr1(struct cpu_user_regs *regs, int regidx)
+{
+ uint32_t vmcr = READ_SYSREG32(ICH_VMCR_EL2);
+ set_user_reg(regs, regidx, __vgic_v3_get_bpr1(vmcr));
+}
+
+static void __vgic_v3_write_bpr1(struct cpu_user_regs *regs, int regidx)
+{
+ register_t val = get_user_reg(regs, regidx);
+ uint8_t bpr_min = __vgic_v3_bpr_min();
+ uint32_t vmcr = READ_SYSREG32(ICH_VMCR_EL2);
+
+ if ( vmcr & ICH_VMCR_CBPR_MASK )
+ return;
+
+ /* Enforce BPR limiting */
+ if ( val < bpr_min )
+ val = bpr_min;
+
+ val <<= ICH_VMCR_BPR1_SHIFT;
+ val &= ICH_VMCR_BPR1_MASK;
+ vmcr &= ~ICH_VMCR_BPR1_MASK;
+ vmcr |= val;
+
+ WRITE_SYSREG32(vmcr, ICH_VMCR_EL2);
+}
+
+void handle_bpr1(struct cpu_user_regs *regs, int regidx, const union hsr hsr)
I am pretty sure I said it in the past. If the function is not exported
it, it *must* be static. I am not going to repeat it and expect all the
sites to be fixed in the next version.
The naming is also a bit odd. All of the file is using "vgic_v3_". So
please try to be consistent.
+{
+ if ( hsr.sysreg.read )
+ __vgic_v3_read_bpr1(regs, regidx);
+ else
+ __vgic_v3_write_bpr1(regs, regidx);
+}
bool vgic_v3_handle_cpuif_access(struct cpu_user_regs *regs, const union hsr hsr)
{
bool ret = true;
+ int regidx = hsr.sysreg.reg;
/* Disabling interrupts to prevent change in guest state */
local_irq_disable();
@@ -35,6 +101,10 @@ bool vgic_v3_handle_cpuif_access(struct cpu_user_regs
*regs, const union hsr hsr
switch ( hsr.bits & HSR_SYSREG_REGS_MASK )
{
+ case HSR_SYSREG_ICC_BPR1_EL1:
+ handle_bpr1(regs, regidx, hsr);
Please use vreg_emulate_* helpers.
+ break;
+
default:
ret = false;
break;
diff --git a/xen/include/asm-arm/arm64/sysregs.h
b/xen/include/asm-arm/arm64/sysregs.h
index 084d2a1e5d..025a27b0b4 100644
--- a/xen/include/asm-arm/arm64/sysregs.h
+++ b/xen/include/asm-arm/arm64/sysregs.h
@@ -89,6 +89,7 @@
#define HSR_SYSREG_ICC_ASGI1R_EL1 HSR_SYSREG(3,1,c12,c11,6)
#define HSR_SYSREG_ICC_SGI0R_EL1 HSR_SYSREG(3,2,c12,c11,7)
#define HSR_SYSREG_ICC_SRE_EL1 HSR_SYSREG(3,0,c12,c12,5)
+#define HSR_SYSREG_ICC_BPR1_EL1 HSR_SYSREG(3,0,c12,c12,3)
#define HSR_SYSREG_CONTEXTIDR_EL1 HSR_SYSREG(3,0,c13,c0,1)
#define HSR_SYSREG_PMCR_EL0 HSR_SYSREG(3,3,c9,c12,0)
diff --git a/xen/include/asm-arm/gic_v3_defs.h
b/xen/include/asm-arm/gic_v3_defs.h
index 65c9dc47cf..68a34cc353 100644
--- a/xen/include/asm-arm/gic_v3_defs.h
+++ b/xen/include/asm-arm/gic_v3_defs.h
@@ -157,6 +157,12 @@
#define GICH_VMCR_EOI (1 << 9)
#define GICH_VMCR_VENG1 (1 << 1)
+#define ICH_VMCR_CBPR_SHIFT 4
+#define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT)
+#define ICH_VMCR_BPR0_SHIFT 21
+#define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
+#define ICH_VMCR_BPR1_SHIFT 18
+#define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
#define GICH_LR_VIRTUAL_MASK 0xffff
#define GICH_LR_VIRTUAL_SHIFT 0
Cheers,
--
Julien Grall
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