Hi,

> On 23 Aug 2021, at 14:22, Julien Grall <[email protected]> wrote:
> 
> 
> 
> On 23/08/2021 13:39, Bertrand Marquis wrote:
>> Hi Julien,
> 
> Hi Bertrand,
> 
>>> On 23 Aug 2021, at 12:47, Julien Grall <[email protected]> wrote:
>>> 
>>> Hi Bertrand,
>>> 
>>> On 23/08/2021 11:32, Bertrand Marquis wrote:
>>>> Replace the code in p2m trying to find a sane value for the VMID size
>>>> supported and the PAR to use. We are now using the boot cpuinfo as the
>>>> values there are sanitized during boot and the value for those
>>>> parameters is now the safest possible value on the system.
>>>> On arm32, the system will panic if there are different types of core so
>>>> those checks were not needed anyway.
>>> 
>>> So the assumption is that if you have the same MIDR, then you must have the 
>>> same features. I understand this is what Xen assumes today but I never 
>>> viewed that check as the truth. It is more to limit the damage on most 
>>> platform.
>> This was the assumption before, I did not change anything but just explained 
>> in the commit message why this was not possible to come to this code.
> 
> Yes. This is not a new, however I thought I would mention it because I want 
> to avoid continuing to use wrong assumptions.
> 
> However, this code is arm64 only as it is #ifdef right? (Sorry I should have 
> looked at the code the first time) So ...
> 
>>> 
>>> So can you confirm whether this is something that Arm guarantees?
>> For a specific MIDR from Arm (ie a Cortex) the PAR is fixed and VMID size to.
>> But for an other Arm architecture processor I cannot say.
>>> 
>>> That said, I am not against removing the code. But I would like the comment 
>>> to be amended if this is not a correct assumption.
>> Would the following be acceptable:
>> On arm32, Xen is not booting on systems having different MIDR amongst cores 
>> and it is assumed that cores with the same MIDR will have the same PAR and 
>> VMID size.
> ... I would just drop any mention of arm32 here.

Ok

Cheers
Bertrand

> 
> Cheers,
> 
> -- 
> Julien Grall


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