On 09.09.2021 13:48, Oleksandr Andrushchenko wrote: > On 09.09.21 12:21, Jan Beulich wrote: >> For the bit in question, where the goal appears to be to have hardware >> hold the OR of guest and host values, an approach similar to that used >> for some of the MSI / MSI-X bits might be chosen: Maintain guest and >> host bits in software, and update hardware (at least) when the >> effective resulting value changes. A complicating fact here is, though, >> that unlike for the MSI / MSI-X bits here Dom0 (pciback or its PCI >> susbstem) may also have a view on what the setting ought to be. > > The bigger question here is what can we take as the reference for INTx > bit, e.g. if Dom0 didn't enable/configured the device being passed through > than its COMMAND register may still be in after reset state and IMO there is > no guarantee it has the values we can say are "as host wants them"
In the absence of Dom0 controlling the device, I think we ought to take Xen's view as the "host" one. Which will want the bit set at least as long as either MSI or MSI-X is enabled for the device. Jan