On 06.12.2021 15:20, Michal Orzel wrote: > to hypervisor when switching to AArch32 state.
Do you perhaps mean "from AArch32 state" (also in further places below? The 64-bit hypervisor runs in AArch64 state in all cases aiui. > --- a/xen/arch/arm/arm64/entry.S > +++ b/xen/arch/arm/arm64/entry.S > @@ -109,8 +109,16 @@ > * If 0, we rely on the on x0/x1 to have been saved at the correct > * position on the stack before. > */ > - .macro entry, hyp, compat, save_x0_x1=1 > + .macro entry, hyp, compat=0, save_x0_x1=1 > sub sp, sp, #(UREGS_SPSR_el1 - UREGS_LR) /* CPSR, PC, SP, LR */ > + > + /* Zero the upper 32 bits of the registers when switching to AArch32 > */ > + .if \compat == 1 /* AArch32 mode */ > + .irp > nr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29 > + mov w\nr, w\nr > + .endr > + .endif Don't you at least want, perhaps even need to respect save_x0_x1 being zero here? Jan
