Re: [PATCH v2 1/5] x86/cpuid: add CPUID flag for Extended Destination ID support

[David Woodhouse]

> /*
>  * With interrupt format set to 0 (non-remappable) bits 55:49 from the
>  * IO-APIC RTE and bits 11:5 from the MSI address can be used to store
>  * high bits for the Destination ID. This expands the Destination ID
>  * field from 8 to 15 bits, allowing to target APIC IDs up 32768.
>  */

I am not keen on that wording because it doesn't seem to fully reflect the
fact that the I/OAPIC is just a device to turn line interrupts into MSIs.
The values in bits 55:49 of the RTE *are* what go into bits 11:5 of the
resulting MSI address. Perhaps make it more parenthetical to make it
clearer that they are not independent... "bits 11:5 of the MSI address
(which come from bits 55:49 of the I/OAPIC RTE)..."


-- 
dwmw2