Wei,
    Thanks for your reply. I will revise that in the next version of the patch.
    To solve the problem that the mail address I send from was not in sync the 
one in the From and S-o-b. I will use another email 
address(davidw...@zhaoxin.com) to resubmit my patch. If necessary, please 
abandon current patch and subject. I am sorry for the trouble.

-----Original Message-----
From: Wei Liu [mailto:wei.l...@citrix.com]
Sent: Friday, March 23, 2018 8:42 PM
To: Fionali <lifang...@126.com>
Cc: xen-devel@lists.xenproject.org; Fiona Li(BJ-RD) <fion...@zhaoxin.com>; 
jbeul...@suse.com; Wei Liu <wei.l...@citrix.com>
Subject: Re: [Xen-devel] [PATCH] x86/cpu: Support a new cpu vendor, which is 
Shanghai. Shanghai cpu defines two msr registers to enable Random Number 
Generator and Advanced Cryprography Engine.The cpu supports iommu, which is 
designed according to Intel's speci...

On Fri, Mar 23, 2018 at 07:28:56PM +0800, Fionali wrote:
> From: FionaLi <fion...@zhaoxin.com>
>
> Signed-off-by: Fiona Li<fion...@zhaoxin.com>
> ---
>  xen/arch/x86/cpu/Makefile         |  1 +
>  xen/arch/x86/cpu/common.c         |  1 +
>  xen/arch/x86/cpu/shanghai.c       | 61 
> +++++++++++++++++++++++++++++++++++++++
>  xen/include/asm-x86/iommu.h       |  2 ++
>  xen/include/asm-x86/msr-index.h   |  4 +++
>  xen/include/asm-x86/setup.h       |  1 +
>  xen/include/asm-x86/x86-vendors.h |  3 +-
>  7 files changed, 72 insertions(+), 1 deletion(-)  create mode 100644
> xen/arch/x86/cpu/shanghai.c
>
> diff --git a/xen/arch/x86/cpu/Makefile b/xen/arch/x86/cpu/Makefile
> index 74f23ae..8fcffdd 100644
> --- a/xen/arch/x86/cpu/Makefile
> +++ b/xen/arch/x86/cpu/Makefile
> @@ -5,6 +5,7 @@ obj-y += amd.o
>  obj-y += centaur.o
>  obj-y += common.o
>  obj-y += intel.o
> +obj-y += shanghai.o
>  obj-y += intel_cacheinfo.o
>  obj-y += mwait-idle.o
>  obj-y += vpmu.o vpmu_amd.o vpmu_intel.o diff --git
> a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index
> 0a452ae..02863c9 100644
> --- a/xen/arch/x86/cpu/common.c
> +++ b/xen/arch/x86/cpu/common.c
> @@ -709,6 +709,7 @@ void __init early_cpu_init(void)
>  intel_cpu_init();
>  amd_init_cpu();
>  centaur_init_cpu();
> +shanghai_init_cpu();
>  early_cpu_detect();
>  }
>
> diff --git a/xen/arch/x86/cpu/shanghai.c b/xen/arch/x86/cpu/shanghai.c
> new file mode 100644 index 0000000..7910f03
> --- /dev/null
> +++ b/xen/arch/x86/cpu/shanghai.c
> @@ -0,0 +1,61 @@
> +#include <xen/lib.h>
> +#include <xen/init.h>
> +#include <xen/bitops.h>
> +#include <asm/processor.h>
> +#include <asm/msr.h>
> +#include <asm/e820.h>

Use the following order please:

 #include <xen/bitops.h>
 #include <xen/init.h>
 #include <xen/lib.h>

 #include <asm/e820.h>
 #include <asm/msr.h>
 #include <asm/processor.h>

> +#include "cpu.h"
> +
> +#define ACE_PRESENT(x)  ((x)&(1U<<6))

Please add spaces around "&" and "<<".

> +#define ACE_ENABLED(x)  ((x)&(1U<<7))
> +#define ACE_FCR(1U << 28)/* MSR_ZX_ACE Advanced Cryprography Engine */
> +
> +#define RNG_PRESENT(x)  ((x)&(1U<<6)) #define RNG_ENABLED(x)
> +((x)&(1U<<7))
> +#define RNG_ENABLE(1U << 6)/* MSR_ZX_RNG Random Number Generator */
> +
> +
> +
> +static void init_shanghai(struct cpuinfo_x86 *c) {
> +uint64_t msr_ace,msr_rng;

Add a blank line here.

> +/* Test for Shanghai Extended CPUID information */
> +if (cpuid_eax(0xC0000000) >= 0xC0000001) {

Coding style. Should be

        if ( XXXX )
{

Please fix all instances.


> +/*Get Shanghai Extended function number */
> +u32 extented_feature_flags = cpuid_edx(0xC0000001);
> +
> +/* enable ACE,if support ACE unit */
> +if(ACE_PRESENT(extented_feature_flags) && 
> !ACE_ENABLED(extented_feature_flags)){
> +rdmsrl(MSR_ZX_ACE, msr_ace);
> +/* enable ACE  */
> +wrmsrl(MSR_ZX_ACE, (msr_ace | ACE_FCR));
> +printk(KERN_INFO "CPU: Enabled ACE h/w crypto\n");

Drop KERN_INFO please.

> +}

Blank line here please.

> +/* enable RNG,if support RNG unit */
> +if (RNG_PRESENT(extented_feature_flags) && 
> !RNG_ENABLED(extented_feature_flags)) {
> +rdmsrl(MSR_ZX_RNG, msr_rng);
> +/* enable RNG  */
> +wrmsrl(MSR_ZX_RNG, msr_rng | RNG_ENABLE);
> +printk(KERN_INFO "CPU: Enabled h/w RNG\n");
> +}
> +}
> +
> +if (c->x86 == 0x6 && c->x86_model >= 0xf) {
> +c->x86_cache_alignment = c->x86_clflush_size * 2;
> +__set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
> +}

Blank line.

> +get_model_name(c);
> +display_cacheinfo(c);
> +}


Wei.


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