Allow disabling (masking) IO-APIC pins set to edge trigger mode. This
is required in order to safely migrate such interrupts between CPUs,
as the write to update the IO-APIC RTE (or the IRTE) is not done
atomically, so there's a window where there's a mismatch between the
destination CPU and the vector:
(XEN) CPU1: No irq handler for vector b5 (IRQ -11, LAPIC)
(XEN) IRQ10 a=0002[0002,0008] v=bd[b5] t=IO-APIC-edge s=00000030
The main risk with masking edge triggered interrupts is losing them,
but getting them injected while in the process of updating the RTE is
equally harmful as the interrupts gets lost anyway.
Signed-off-by: Roger Pau Monné <roger....@citrix.com>
---
xen/arch/x86/io_apic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/xen/arch/x86/io_apic.c b/xen/arch/x86/io_apic.c
index c086f40f63..2e5964640b 100644
--- a/xen/arch/x86/io_apic.c
+++ b/xen/arch/x86/io_apic.c
@@ -1782,7 +1782,7 @@ static hw_irq_controller ioapic_edge_type = {
.startup = startup_edge_ioapic_irq,
.shutdown = irq_shutdown_none,
.enable = unmask_IO_APIC_irq,
- .disable = irq_disable_none,
+ .disable = mask_IO_APIC_irq,
.ack = ack_edge_ioapic_irq,
.set_affinity = set_ioapic_affinity_irq,
};
--
2.35.1
