On Tue, Apr 26, 2022 at 12:05:07PM +0200, Jan Beulich wrote: > From: Artem Bityutskiy <artem.bityuts...@linux.intel.com> > > Add Sapphire Rapids Xeon support. > > Up until very recently, the C1 and C1E C-states were independent, but this > has changed in some new chips, including Sapphire Rapids Xeon (SPR). In these > chips the C1 and C1E states cannot be enabled at the same time. The "C1E > promotion" bit in 'MSR_IA32_POWER_CTL' also has its semantics changed a bit. > > Here are the C1, C1E, and "C1E promotion" bit rules on Xeons before SPR. > > 1. If C1E promotion bit is disabled. > a. C1 requests end up with C1 C-state. > b. C1E requests end up with C1E C-state. > 2. If C1E promotion bit is enabled. > a. C1 requests end up with C1E C-state. > b. C1E requests end up with C1E C-state. > > Here are the C1, C1E, and "C1E promotion" bit rules on Sapphire Rapids Xeon. > 1. If C1E promotion bit is disabled. > a. C1 requests end up with C1 C-state. > b. C1E requests end up with C1 C-state. > 2. If C1E promotion bit is enabled. > a. C1 requests end up with C1E C-state. > b. C1E requests end up with C1E C-state. > > Before SPR Xeon, the 'intel_idle' driver was disabling C1E promotion and was > exposing C1 and C1E as independent C-states. But on SPR, C1 and C1E cannot be > enabled at the same time. > > This patch adds both C1 and C1E states. However, C1E is marked as with the > "CPUIDLE_FLAG_UNUSABLE" flag, which means that in won't be registered by > default. The C1E promotion bit will be cleared, which means that by default > only C1 and C6 will be registered on SPR. > > The next patch will add an option for enabling C1E and disabling C1 on SPR. > > Signed-off-by: Artem Bityutskiy <artem.bityuts...@linux.intel.com> > Signed-off-by: Rafael J. Wysocki <rafael.j.wyso...@intel.com> > Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git > 9edf3c0ffef0 > Signed-off-by: Jan Beulich <jbeul...@suse.com>
Acked-by: Roger Pau Monné <roger....@citrix.com> Thanks, Roger.
