Re: [PATCH v2] x86/msr: handle reads to MSR_P5_MC_{ADDR,TYPE}

[Roger Pau Monné]

On Thu, Apr 28, 2022 at 12:39:19PM +0200, Jan Beulich wrote:
> On 28.04.2022 11:13, Roger Pau Monne wrote:
> > --- a/xen/arch/x86/cpu/mcheck/mce_intel.c
> > +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
> > @@ -1008,8 +1008,24 @@ int vmce_intel_wrmsr(struct vcpu *v, uint32_t msr, 
> > uint64_t val)
> >  
> >  int vmce_intel_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val)
> >  {
> > +    const struct cpuid_policy *cp = v->domain->arch.cpuid;
> >      unsigned int bank = msr - MSR_IA32_MC0_CTL2;
> >  
> > +    switch ( msr )
> > +    {
> > +    case MSR_P5_MC_ADDR:
> > +        /* Bank 0 is used for the 'bank 0 quirk' on older processors. */
> > +        *val = v->arch.vmce.bank[1].mci_addr;
> > +        return 1;
> > +
> > +    case MSR_P5_MC_TYPE:
> > +        *val = v->arch.vmce.bank[1].mci_status;
> > +        return 1;
> > +    }
> 
> Could I ask you to add a reference to vcpu_fill_mc_msrs() in the comment?

Sure.

Thanks, Roger.