On 13/04/18 09:39, Jan Beulich wrote: >>>> On 12.04.18 at 18:55, <andrew.coop...@citrix.com> wrote: >> @@ -2029,7 +2035,17 @@ long set_debugreg(struct vcpu *v, unsigned int reg, >> unsigned long value) >> if ( v == curr ) >> write_debugreg(3, value); >> break; >> + >> + case 4: >> + if ( v->arch.pv_vcpu.ctrlreg[4] & X86_CR4_DE ) >> + return -ENODEV; >> + >> + /* Fallthrough */ >> case 6: >> + /* The upper 32 bits are strictly reserved. */ >> + if ( value != (uint32_t)value ) >> + return -EINVAL; >> + >> /* >> * DR6: Bits 4-11,16-31 reserved (set to 1). >> * Bit 12 reserved (set to 0). > How are the upper 32 bits different from the other reserved bits (named in the > comment visible here)?
The upper 32 bits are MBZ and will raise #GP if set. The lower reserved bits are write-ignored. ~Andrew _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel